論文誌
[1]  Constantin Siriteanu, Satoshi Kuriki, Donald Richards, and Akimichi Takemura, ``Chi-Square Mixture Representations for the Distribution of the Scalar Schur Complement in a Noncentral Wishart Matrix,'' Statistics and Probability Letters, accepted, February 2016.
[2]  D. Fukuda, K. Watanabe, Y. Kanazawa, and M. Hashimoto, ``Modeling the Effect of Global Layout Pattern on Wire Width Variation for On-The-Fly Etching Process Modification,'' IEICE Trans. Fundamentals of Electronics Communications and Computer Sciences, vol. E98-A, no. 7, pp. 1467--1474, July 2015.
[3]  H. Konoura, D. Alnajjar, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, K. Wakabayashi, M. Hashimoto, T. Onoye, and H. Onodera, ``Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E97-A, no. 12, pp. 2518--2529, December 2014.
[4]  H. Konoura, T. Imagawa, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Comparative Evaluation of Lifetime Enhancement with Fault Avoidance on Dynamically Reconfigurable Devices,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E97-A, no. 7, pp. 1468--1482, July 2014.
[5]  H. Fuketa, R. Harada, M. Hashimoto, and T. Onoye, ``Measurement and Analysis of Alpha-Particle-Induced Soft Errors and Multiple Cell Upsets in 10t Subthreshold Sram,'' IEEE Transactions on Device and Materials Reliability, vol. 14, no. 1, p. 463 -- 470, March 2014.
[6]  D. Alnajjar, H. Konoura, Y. Ko, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Implementing Flexible Reliability in a Coarse Grained Reconfigurable Architecture,'' IEEE Transactions on VLSI Systems, vol. 21, no. 12, p. 2165 -- 2178, December 2013.
[7]  T. Uemura, T. Kato, H. Matsuyama, and M. Hashimoto, ``Mitigating Multi-Bit-Upset with Well-Slits in 28 Nm Multi-Bit-Latch,'' IEEE Transactions on Nuclear Science, vol. 60, no. 6, pp. 4362--4367, December 2013.
[8]  M. Okada, M. Hatanaka, K. Kagawa, and S. Miyamoto, ``Realization of Secure Ambient Wireless Network System Based on Spatially Distributed Ciphering Function,'' IEICE Trans. on Fundamentals of Electronics, vol. E96-A, no. 11, November 2013.
[9]  R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Impact of NBTI-Induced Pulse-Width Modulation on SET Pulse-Width Measurement,'' IEEE Transactions on Nuclear Science, vol. 60, no. 4, pp. 2630--2634, August 2013.
[10]  T. Amaki, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``A Worst-Case-Aware Design Methodology for Noise-Tolerant Oscillator-Based True Random Number Generator with Stochastic Behavior Modeling,'' IEEE Transactions on Information Forensics and Security, vol. 8, no. 8, pp. 1331--1342, August 2013.
[11]  D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Pvt-Induced Timing Error Detection Through Replica Circuits and Time Redundancy in Reconfigurable Devices,'' IEICE Electronics Express (ELEX), vol. 10, no. 5, April 2013.
[12]  T. Amaki, M. Hashimoto, and T. Onoye, ``Jitter Amplifier for Oscillator-Based True Random Number Generator,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E96-A, no. 3, pp. 684--696, March 2013.
[13]  I. Homjakovs, M. Hashimoto, T. Hirose, and T. Onoye, ``Signal-Dependent Analog-To-Digital Conversion Based on Minimax Sampling,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E96-A, no. 2, pp. 459--468, February 2013.
[14]  劉載勲, 宮本龍介, 尾上孝雄, ``CoHOG特徴を用いた歩行者検出の確率的サンプリングに基づく高速化,'' 画像電子学会誌, vol. 42, no. 1, pp. 30-40, January 2013.
[15]  S. Kimura, M. Hashimoto, and T. Onoye, ``A Body Bias Clustering Method for Low Test-Cost Post-Silicon Tuning,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E95-A, no. 12, pp. 2292--2300, December 2012.
[16]  Ryusuke Endo, Yuichi Itoh, Kosuke Nakajima, Kazuyuki Fujita, Fumio Kishino, ``Digital Signage Supporting Collaborative Route Planning in Real Commercial Establishment,'' ICIC Express Letters, vol. 6, no. 12, pp. 2967-2972, December 2012.
[17]  H. Konoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Stress Probability Computation for Estimating NBTI-Induced Delay Degradation,'' IEICE Trans. Fundamentals, vol. E94-A, no. 12, pp. 2545-2553, December 2011.
[18]  H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``Transistor Variability Modeling and Its Validation with Ring-Oscillation Frequencies for Body-Biased Subthreshold Circuits,'' IEEE Transactions on VLSI Systems, vol. 18, no. 7, pp. 1118--1129, July 2010.
[19]  密山 幸男, 高橋 一真, 今井 林太郎, 橋本 昌宜, 尾上 孝雄, 白川 功, ``メディア処理向け再構成可能アーキテクチャでの動画像復号処理の実現,'' 電子情報通信学会論文誌, vol. J93-A, no. 6, pp. 397-413, June 2010.
[20]  渡邊 賢治, 達可 敏充, 畠中 理英, 尾上 孝雄, ``屋内位置推定システムのための間取り推定手法,'' Journal of Signal Processing, vol. 14, no. 3, pp. 231-242, May 2010.
[21]  K. Shinkai, M. Hashimoto, and T. Onoye, ``Prediction of Self-Heating in Short Intra-Block Wires,'' IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, vol. E93-A, no. 3, pp. 583-594, March 2010.
[22]  T. Sakata, T. Okumura, A. Kurokawa, H. Nakashima, H. Masuda, T. Sato, M. Hashimoto, K. Hachiya, K. Furukawa, M. Tanaka, H. Takafuji, and T. Kanamoto, ``An Approach for Reducing Leakage Current Variation Due to Manufacturing Variability,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E92-A, no. 12, pp. 3016--3023, December 2009.
[23]  Y. Ogasahara, M. Hashimoto, and T. Onoye, ``All Digital Ring-Oscillator Based Macro for Sensing Dynamic Supply Noise Waveform,'' IEEE Journal of Solid-State Circuits, vol. 44, no. 6, pp. 1745--1755, June 2009.
[24]  T. Enami, S. Ninomiya, and M. Hashimoto, ``Statistical Timing Analysis Considering Spatially and Temporally Correlated Dynamic Power Supply Noise,'' IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 4, pp. 541-553, April 2009.
[25]  K. Hamamoto, H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``An Experimental Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability,'' IEICE Trans. on Electronics, vol. E92-C, no. 2, pp. 281-285, February 2009.
[26]  S. Abe, M. Hashimoto, and T. Onoye, ``Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E91-A, no. 12, pp. 3481-3487, December 2008.
[27]  Nobuyuki Iwanaga, Tomoya Matsumura, Akihiro Yoshida, Wataru Kobayashi, and Takao Onoye, ``Embedded System Implementation of Sound Localization in Proximal Region,'' IEICE Trans. Fundamentals, vol. E91-A, no. 3, pp. 763-771, March 2008.
[28]  Y. Ogasahara, M. Hashimoto, and T. Onoye, ``Measurement and Analysis of Inductive Coupling Noise in 90nm Global Interconnects,'' IEEE Journal of Solid-State Circuits, vol. 43, no. 3, pp. 718-728, March 2008.
[29]  Y. Ogasahara, T. Enami, M. Hashimoto, T. Sato, and T. Onoye, ``Validation of a Full-Chip Simulation Model for Supply Noise and Delay Dependence on Average Voltage Drop with On-Chip Delay Measurement,'' IEEE Trans. on Circuits and Systems—II: Express Briefs, vol. 54, no. 10, pp. 868-872, October 2007.
[30]  K. Tsujino, W. Kobayashi, T. Onoye, and Y. Nakamura, ``Automatic Filter Design for 3-D Sound Movement in Embedded Applications,'' In Acoustical Science and Technology, vol. 28, no. 4, pp. 219-229, July 2007.
[31]  M. Ise, Y. Ogasahara, K. Watanabe, M. Hatanaka, T. Onoye, H. Niwamoto, I. Keshi, and I. Shirakawa, ``Design and Implementation of Home Network Protocol for Appliance Control Based on IEEE 802.15.4,'' International Journal of Computer Science and Network Security, vol. 7, no. 7, pp. 20-30, July 2007.
[32]  T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, and M. Hashimoto, ``Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in Soc Design,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E89-A, no. 12, pp. 3560--3568, December 2006.
[33]  T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, and M. Hashimoto, ``Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in Soc Design,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E89-A, no. 12, pp. 3560-3568, December 2006.
[34]  T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, and M. Hashimoto, ``Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in Soc Design,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E89-A, no. 12, pp. 3560-3568, December 2006.
[35]  M. Ise, Y. Ogasahara, T. Onoye, and I. Shirakawa, ``W-CDMA Channel Codec by Configurable Processors,'' In Intelligent Automation and Soft Computing, vol. 12, no. 3, pp. 317--29, 2006.
[36]  A. Tsuchiya, M. Hashimoto, and H. Onodera, ``Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Science, vol. E88-A, no. 4, pp. 885-891, April 2005.
[37]  S. Tani, Y. Uchida, M. Furuie, S. Tsukiyama, B. Lee, S. Nishi, Y. Kubota, I. Shirakawa, and S. Imai, ``Parasitic Capacitance Modeling for Non-Planar Interconnects in Liquid Crystal Displays,'' IEICE Trans. on Fundamentals, vol. E86-A, no. 12, pp. 2923--2932, December 2003.
[38]  小谷 章夫, 小山 至幸, 密山 幸男, 尾上 孝雄, ``低解像度表示デバイス向けフォント "LCFONT" の重心位置および可読性評価,'' 画像電子学会誌, vol. 32, no. 5, pp. 621--628, September 2003.
[39]  岡田 浩行, 宋 学燮, 藤田 玄, 尾上 孝雄, 白川 功, ``電子透かしのMPEG-4ビットストリームエラー検出への応用,'' 画像電子学会誌, vol. 31, no. 5, pp. 900--908, September 2002.
[40]  Hiroshi Tsutsui, Akihiko Tomita, Shigenori Sugimoto, Kazuhisa Sakai, Tomonori Izumi, Takao Onoye, and Yukihiro Nakamura, ``Lut-Array-Based Pld and Synthesis Approach Based on Sum of Generalized Complex Terms Expression,'' IEICE Trans. Fundamentals, vol. E84-A, no. 11, pp. 2681-2689, November 2001.
[41]  W. Kobayashi, N. Sakamoto, T. Onoye, and I. Shirakawa, ``3D Acoustic Image Localization Algorithm by Embedded DSP,'' IEICE(The Institute of Electronics, Information and Communication Engineers) Trans. Fundamentals of Electronics Communications and Computer Sciences, vol. E84-A, no. 6, pp. 1423--1430, June 2001.
[42]  T. Watanabe and N. Ishiura, ``Resister Constraint Analysis to Minimize Spill Code for Application Specific DSPs,'' IEICE Trans. Fundamentals of Electronics Communications and Computer Sciences, vol. E84-A, no. 6, pp. 1541--1544, June 2001.
[43]  K. Kawamoto, S. Mizuno, H. Abe, Y. Higuchi, H. Ishihara, H. Fukumoto, T. Watanabe, S. Fujino, and I. Shirakawa, ``A Single Chip Automotive Control LSI Using SOI Bipolar Complimentary MOS Double-Diffused MOS,'' The Japan Society of Applied Physics, vol. 40, no. 4B, pp. 2891--2896, April 2001.
[44]  A. Nagao, I. Shirakawa, and T. Kambe, ``A Layout Approach to Monolithic Microwave IC,'' IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 17, no. 12, pp. 1262--1272, December 1998.
[45]  S. Yano, K. Akagi, H. Inohara, and N. Ishiura, ``Application of Full Scan Design to Embedded Memory Arrays,'' in Proc. IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, vol. E80-A, no. 3, March 1997.
[46]  Y. Shigehiro, T. Nagata, I. Shirakawa, I. Arungsrisangchai, and H. Takahashi, ``Automatic Layout Recycling Based on Layout Description and Linear Programming,'' in Proc. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 15, no. 8, pp. 959-967, August 1996.
国際会議
[1]  U. Schlichtmann, M. Hashimoto, I. H.-R. Jiang, and B. Li, ``Reliability, Adaptability and Flexibility in Timing: Buy a Life Insurance for Your Circuits (Invited),'' Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 705--711, January 2016.
[2]  N. Banno, M.Tada, K. Okamoto, N. Iguchi, T. Sakamoto, M. Miyamura, Y. Tsuji, H. Hada, H. Ochi, H. Onodera, M. Hashimoto, and T. Sugibayashi Author(s) in English , ``A Novel Two-Varistors (A-Si/Sin/A-Si) Selected Complementary Atom Switch (2v-1cas) for Nonvolatile Crossbar Switch with Multiple Fan-Outs,'' Technical Digest of IEEE International Electron Devices Meeting (IEDM), pp. 32--35, December 2015.
[3]  Y. Masuda, M. Hashimoto, and T. Onoye, ``Performance Evaluation of Software-Based Error Detection Mechanisms for Localizing Electrical Timing Failures under Dynamic Supply Noise,'' In Proceedings of International Conference on Computer-Aided Design (ICCAD), pp. 315-322, November 2015.
[4]  R. Doi, M. Hashimoto, and T. Onoye, ``An Analytic Evaluation on Soft Error Immunity Enhancement Due to Temporal Triplication,'' IEEE Pacific Rim International Symposium on Dependable Computing (PRDC), November 2015.
[5]  E. Aliwarga, J. Yu, M. Hatanaka, and T. Onoye, ``Design of Generic Hardware for Soft Cascade-Based Linear Svm Classification,'' In International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), pp. 257-262, November 2015.
[6]  M. Ueno, M. Hashimoto, and T. Onoye, ``Real-Time On-Chip Supply Voltage Sensor and Its Application to Trace-Based Timing Error Localization,'' Proceedings of International On-Line Testing Symposium (IOLTS), pp. 188--193, July 2015.
[7]  T. Uemura, T. Kato, S. Okano, H. Matsuyama, and M. Hashimoto, ``Impact of Package on Neutron Induced Single Event Upset in 20 Nm Sram,'' Proceedings of International Symposium on Reliability Physics (IRPS), April 2015.
[8]  T. Uemura and M. Hashimoto, ``Investigation of Single Event Upset and Total Ionizing Dose in Feram for Medical Electronic Tag,'' Proceedings of International Symposium on Reliability Physics (IRPS), April 2015.
[9]  T. Uemura, S. Okano, T. Kato, H. Matsuyama, and M. Hashimoto, ``Soft Error Immune Latch Design for 20 Nm Bulk Cmos,'' Proceedings of International Reliability Physics Symposium (IRPS), April 2015.
[10]  M. Hashimoto, D. Alnajjar, H. Konoura, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, K. Wakabayashi, T. Onoye, and H. Onodera, ``Reliability-Configurable Mixed-Grained Reconfigurable Array Compatible with High-Level Synthesis,'' Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 14--15, January 2015.
[11]  M. Hashimoto, ``Toward Robust Subthreshold Circuit Design: Variability and Soft Error Perspective (Invited),'' Proceedings of SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), October 2014.
[12]  A. Iokibe, M. Hashimoto, and T. Onoye, ``Feasibility Evaluation on an Instant Invader Detection System with Ultrasonic Sensors Scattered on the Ground,'' Proceedings of International Conference on Sensing Technology (ICST), pp. 188--193, September 2014.
[13]  T. Uemura, T. Kato, R. Tanabe, H. Iwata, H. Matsuyama, M. Hashimoto, K. Takahisa, M. Fukuda, and K. Hatanaka, ``Preventing Single Event Latchup with Deep P-Well on P-Substrate,'' Proceedings of International Reliability Physics Symposium (IRPS), June 2014.
[14]  M. Ueno, M. Hashimoto, and T. Onoye, ``Trace-Based Fault Localization with Supply Voltage Sensor,'' ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), March 2014.
[15]  C.Siriteanu, A.Takemura, S.D. Blostein, S.Kuriki, and H.Shin, ``Convergence Analysis of Performance-Measure Expressions for Mimo Zf under Rician Fading,'' Australian Communications Theory Workshop, AUSCTW'14, Sydney, Australia, pp. 114-119 , February 2014.
[16]  Hiroaki Konoura, Dawood Alnajjar, Yukio Mitsuyama, Hiroyuki Ochi, Takashi Imagawa, Shinichi Noda, Kazutoshi Wakabayashi, Masanori Hashimoto, and Takao Onoye, ``Mixed-Grained Reconfigurable Architecture Supporting Flexible Reliability and C-Based Design,'' In ReConFig, December 2013.
[17]  D. Alnajjar, H. Konoura, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, S. Noda, K. Wakabayashi, M. Hashimoto, T. Onoye, and H. Onodera, ``Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-To-Array Mapping and Its Radiation Testing,'' In Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 313-316, November 2013.
[18]  T. Amaki, M. Hashimoto, and T. Onoye, ``A Process and Temperature Tolerant Oscillator-Based True Random Number Generator with Dynamic 0/1 Bias Correction,'' In Proceedings of Asian Solid-State Circuits Conference (A-SSCC), pp. 133-136, November 2013.
[19]  J. Kono, M. Hashimoto, and T. Onoye, ``Feasibility Evaluation of Near-Field Communication in Clay with 1-Mm^3 Antenna,'' Proceedings of Asia-Pacific Microwave Conference (APMC), pp. 1121--1123, November 2013.
[20]  R. Harada, M. Hashimoto, and T. Onoye, ``Nbti Characterization Using Pulse-Width Modulation,'' IEEE/ACM Workshop on Variability Modeling and Characterization, November 2013.
[21]  Simon Voelker, Kosuke Nakajima, Christian Thoresen, Yuichi Itoh, Kjell Ivar Øvergård, and Jan Borchers, ``Pucs: Detecting Transparent, Passive Untouched Capacitive Widgets on UnmodifiEd Multi-Touch Displays,'' In Adjunct Publication of the 26th Annual ACM Symposium on User Interface Software and Technology, pp. 1-2, October 2013.
[22]  T. Uemura, T. Kato, H. Matsuyama, and M. Hashimoto, ``Scaling Trend of Sram and Ff of Soft-Error Rate and Their Contribution to Processor Reliability on Bulk Cmos Technology,'' IEEE Nuclear and Space Radiation Effects Conference (NSREC), July 2013.
[23]  T. Uemura, T. Kato, H. Matsuyama, and M. Hashimoto, ``Mitigating Multi-Cell-Upset with Well-Slits in 28nm Multi-Bit-Latch,'' IEEE Nuclear and Space Radiation Effects Conference (NSREC), July 2013.
[24]  T. Shinada, M. Hashimoto, and T. Onoye, ``Proximity Distance Estimation Based on Capacitive Coupling between 1mm^3 Sensor Nodes,'' Proceedings of International NEWCAS Conference, June 2013.
[25]  M. Hashimoto, ``Robust Subthreshold Circuit Design to Manufacturing and Environmental Variability (Invited),'' China Semiconductor Technology International Conference (CSTIC), pp. 1079--1084, March 2013.
[26]  Jin Kono, Masanori Hashimoto, Takao Onoye, ``Feasibility Evaluation of Near-Field Communication in Clay with 1-Mm3 Antenna,'' Microwave Conference Proceedings (APMC), 2013 Asia-Pacific, pp. 1121-1123, 2013.
[27]  D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Static Voltage Over-Scaling and Dynamic Voltage Variation Tolerance with Replica Circuits and Time Redundancy in Reconfigurable Devices,'' Proceedings of International Conference on ReConFigurable Computing and FPGAs (ReConFig), December 2012.
[28]  I. Homjakovs, M. Hashimoto, T. Hirose, and T. Onoye, ``Signal-Dependent Analog-To-Digital Converter Based on Minimax Sampling,'' Proceedings of International SoC Design Conference (ISOCC), p. 120 -- 123 , November 2012.
[29]  Kazuki Takashima, Yusuke Hayashi, Kosuke Nakajima, and Yuichi Itoh, ``Cup-Embedded Information Device for Supporting Interpersonal Communication,'' In Proceedings of Joint Virtual Reality Conference of ICAT, EGVE and EuroVR, pp. 19-20, October 2012.
[30]  T. Kameda, H. Konoura, D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``A Predictive Delay Fault Avoidance Scheme for Coarse-Grained Reconfigurable Architecture,'' Proceedings of International Conference on Field Programmable Logic and Applications (FPL) , August 2012.
[31]  R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Set Pulse-Width Measurement Eliminating Pulse-Width Modulation and Within-Die Process Variation Effects,'' Proceedings of International Reliability Physics Symposium (IRPS), April 2012.
[32]  K. Watanabe, G. Fujita, T. Homemoto, and R. Hashimoto, ``A High-Speed H.264/AVC CABAC Decoder for 4K Video Utilizing Residual Data Accelerator,'' The 17th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2012), pp. 6-10, March 2012.
[33]  S. Kimura, M. Hashimoto, and T. Onoye, ``Body Bias Clustering for Low Test-Cost Post-Silicon Tuning,'' In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 283--289, February 2012.
[34]  Takashi Nakamae, Akihisa Yamada, Masayuki Yamaguchi, and Takao Onoye, ``A Near-Lossless Image Compression Method Using Adaptive Variable Length Coding,'' In International Conference on Embedded Systems and Intelligent Technology, January 2012.
[35]  K. Kiyokawa, M. Hatanaka, K. Hosoda, M. Okada, H. Shigeta, Y. Ishihara, F. Ooshita, H. Kakugawa, S. Kurihara, and K. Moriyama, ``Owens Luis - a Proposal of a Smart Office Chair in an Ambient Environment,'' In The 21st International Conference on Artificial Reality and Telexistence (ICAT 2011), Osaka, Japan, November 2011.
[36]  H. Konoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Implications of Reliability Enhancement Achieved by Fault Avoidance on Dynamically Reconfigurable Architectures,'' In Proc. 21st International Conference on Field Programmable Logic and Applications (FPL2011), Chania, Crete, Greece, pp. 189-194, September 2011.
[37]  I. Homjakovs, M. Hashimoto, T. Hirose, and T. Onoye, ``Signal-Dependent Analog-To-Digital Conversion Based on Minimax Sampling,'' In Proceedings of International Midwest Symposium on Circuits and Systems (MWSCAS), August 2011.
[38]  T. Amaki, M. Hashimoto, and T. Onoye, ``An Oscillator-Based True Random Number Generator with Jitter Amplifier,'' In Proc. IEEE International Symposium on Circuits and Systems (ISCAS 2011), pp. 725-728, May 2011.
[39]  R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Neutron Induced Single Event Multiple Transients with Voltage Scaling and Body Biasing,'' In Proc. International Reliability Physics Symposium (IRPS), April 2011.
[40]  S. Kimura, M. Hashimoto, and T. Onoye, ``Body Bias Clustering for Low Test-Cost Post-Silicon Tuning,'' In ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pp. 46--51, April 2011.
[41]  D. Alnajjar, H. Kounoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Mttf Measurement under Alpha Particle Radiation in a Coarse-Grained Reconfigurable Architecture with Flexible Reliability,'' In IEEE Workshop on Silicon Errors in Logic - System Effects, March 2011.
[42]  Tatsuo Maeno, Hiroshi Tsutsui, and Takao Onoye, ``Hardware Implementation of Real-Time Motion Adaptive Deinterlacing Based on Inpainting,'' In International Conference on Embedded Systems and Intelligent Technology, February 2011.
[43]  T. Amaki, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``A Design Procedure for Oscillator-Based Hardware Random Number Generator with Stochastic Behavior Modeling,'' In Proc. International Workshop on Information Security Applications (WISA 2010), pp. 107-121, January 2011.
[44]  T. Amaki, M. Hashimoto, and T. Onoye, ``Jitter Amplifier for Oscillator-Based True Random Number Generator,'' In Proc. Asia and South Pacific Design Automation Conference (ASP-DAC 2011), pp. 81-82, January 2011.
[45]  K. Shinkai and M. Hashimoto, ``Device-Parameter Estimation with On-Chip Variation Sensors Considering Random Variability,'' In Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 683-688, January 2011.
[46]  M. Hatanaka, R. Hashimoto, T. Tatsuka, T. Onoye, H. Hatamoto, S. Ibi, S. Miyamoto, and S. Sampei, ``VLSI Design of OFDM Baseband Transceiver with Dynamic Spectrum Access,'' In Proc. of the 18th International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS2010), pp. 329-332, December 2010.
[47]  L. M. Handaya, M. Okada, T. Onoye, and W. Kobayashi, ``Improvement of Frontal Localization with Complement of Multiple Delayed Sounds,'' 2010 International Workshop on Information Communication Technology, August 2010.
[48]  K. Shinkai and M. Hashimoto, ``Self-Heating in Nano-Scale Vlsi Interconnects,'' In Proceedings of International Workshop on Information Communication Technology (ICT), pp. S-1-6, August 2010.
[49]  S. Abe, K. Shinkai, M. Hashimoto, and T. Onoye, ``Clock Skew Reduction by Self-Compensating Manufacturing Variability with On-Chip Sensors,'' In Proc. Great Lakes Symposium on VLSI (GLSVLSI), May 2010.
[50]  H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``Alpha-Particle-Induced Soft Errors and Multiple Cell Upsets in 65-Nm 10t Subthreshold Sram,'' In Proceedings of International Reliability Physics Symposium (IRPS), pp. 213--217, May 2010.
[51]  H. Konoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Comparative Study on Delay Degrading Estimation Due to Nbti with Circuit/Instance/Transistor-Level Stress Probability Consideration,'' In Proc. International Symposium on Quality Electronic Design (ISQED), pp. 646-651, March 2010.
[52]  R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Measurement Circuits for Acquiring SET Pulse Width Distribution with Sub-FO1-Inverter-Delay Resolution,'' In Proc. International Symposium on Quality Electronic Design (ISQED), March 2010.
[53]  S. Abe, K. Shinkai, M. Hashimoto, and T. Onoye, ``Clock Skew Reduction by Self-Compensating Manufacturing Variability with On-Chip Sensors,'' In Proc. International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), March 2010.
[54]  Koichi Hattori, Hiroshi Tsutsui, Hiroyuki Ochi, and Yukihiro Nakamura, ``A High-Throughput Pipelined Architecture for JPEG XR Encoding,'' In Proc. of 7th IEEE Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia2009) , pp. 9-17, October 2009. (Best Paper Award)
[55]  S. Ninomiya and M. Hashimoto, ``Enhancement of Grid-Based Spatially-Correlated Variability Modeling for Improving Ssta Accuracy,'' In Proceedings of IEEE International SOC Conference (SOCC), pp. 337--340, September 2009.
[56]  K. Hamamoto, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``Tuning-Friendly Body Bias Clustering for Compensating Random Variability in Subthreshold Circuits,'' In Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), pp. 51--56, August 2009.
[57]  D. Alnajjar, Y. Ko, T. Imagawa, H. Konoura, M. Hiromoto, Y. Mitsuyama, M. Hashimoto, H. Ochi, and T. Onoye, ``Coarse-Grained Dynamically Reconfigurable Architecture with Flexible Reliability,'' In Proceedings of International Conference on Field Programmable Logic and Applications (FPL), pp. 186--192, August 2009.
[58]  M. Okada, N. Iwanaga, T. Matsumura, T. Onoye, and W. Kobayashi, ``An Embedded Sound Localization System for Multiple Sources by Fuzzy Clustering with Spatial Constraints,'' In 2009 International Workshop on Nonlinear Circuits and Signal Processing (NCSP '09), Waikiki, Hawaii, pp. 257-260, March 2009.
[59]  S. Watanabe, M. Hashimoto, and T. Sato, ``A Case for Exploiting Complex Arithmetic Circuits Towards Performance Yield Enhancement,'' In Proceedings of International Symposium on Quality Electronic Design (ISQED), pp. 401--407, March 2009.
[60]  Y. Ko, D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Coarse-Grained Dynamically Reconfigurable Architecture with Flexible Reliability,'' In Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pp. 236--241, March 2009.
[61]  D. Alnajjar, Y. Ko, T. Imagawa, M. Hiromoto, Y. Mitsuyama, M. Hashimoto, H. Ochi, and T. Onoye, ``A Coarse-Grained Dynamically Reconfigurable Architecture Enabling Flexible Reliability,'' In Proceedings of IEEE Workshop on System Effects of Logic Soft Errors (SELSE), March 2009.
[62]  K. Shinkai and M. Hashimoto, ``A Gate Delay Model Focusing on Current Fluctuation Over Wide-Range of Process and Environmental Variability,'' In Proc. International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pp. 79-84, February 2009.
[63]  L. Zhang, Y. Zhang, A. Tsuchiya, M. Hashimoto, E. Kuh, and C-K Cheng, ``High Performance On-Chip Differential Signaling Using Passive Compensation for Global Communication,'' In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 385--390, January 2009.
[64]  M. Okada, N. Iwanaga, T. Matsumura, T. Onoye, and W. Kobayashi, ``A 3D Sound Localization Method for Multiple Sound Sources Based on Fuzzy Clustering,'' In 2008 International Workshop on Smart Info-Media Systems in Bangkok (SISB 2008), pp. 133-138, December 2008.
[65]  T. Enami, M. Hashimoto, and T. Sato, ``Decoupling Capacitance Allocation for Timing with Statistical Noise Model and Timing Analysis,'' In Proc. IEEE/ACM International Conference on Computer-Aided Design, pp. 420-425, November 2008.
[66]  H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``Vth Variation Modeling and Its Validation with Ring Oscillation Frequencies for Body-Biased Circuits and Subthreshold Circuits,'' In ICCAD Colocated Workshop on Test Structure Design for Variability Characterization, November 2008.
[67]  Y. Ogasahara, M. Hashimoto, T. Kanamoto, and T. Onoye, ``Measurement of Supply Noise Suppression by Substrate and Deep N-Well in 90nm Process,'' In Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 397--400, November 2008.
[68]  H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``Correlation Verification between Transistor Variability Model with Body Biasing and Ring Oscillation Frequency in 90nm Subthreshold Circuits,'' In Proc. IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), pp. 3-8, August 2008.
[69]  S. Watanabe, M. Hashimoto, and T. Sato, ``Cascading Dependent Operations for Mitigating Timing Variability,'' In Proceedings. of Workshop on Quality-Aware Design (W-QUAD), June 2008.
[70]  K. Hamamoto, H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``Experimental Study on Body-Biasing Layout Style - Negligible Area Overhead Enables Sufficient Speed Controllability -,'' In ACM Great Lakes Symposium on VLSI, pp. 387-390, May 2008.
[71]  T. Enami, S. Ninomiya, and M. Hashimoto, ``Statistical Timing Analysis Considering Spatially and Temporally Correlated Dynamic Power Supply Noise,'' In Proc. ACM International Symposium on Physical Design, pp. 160-167, April 2008.
[72]  S. Abe, M. Hashimoto, and T. Onoye, ``Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution,'' In Proc. International Symposium on Quality Electronic Design (ISQED), pp. 520-525, March 2008.
[73]  K.Hamamoto, H.Fuketa, M.Hashimoto, Y.Mitsuyama, and T.Onoye, ``A Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability,'' In Proc. Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI 2007), pp. 233-237, October 2007.
[74]  T. Kanamoto, Y. Ogasahara, K. Natsume, K. Yamaguchi, H. Amishiro, T. Watanabe, and M. Hashimoto, ``Impact of Well Edge Proximity Effect on Timing,'' In Proc. IEEE European Solid-State Device Research Conference, pp. 115-118, September 2007.
[75]  M. Hashimoto, J. Siriporn, A. Tsuchiya, H. Zhu, and C.-K. Cheng, ``Analytical Eye-Diagram Model for On-Chip Distortionless Transmission Lines and Its Application to Design Space Exploration,'' In Proc. IEEE Custom Integrated Circuits Conference, pp. 869-872, September 2007.
[76]  K. Shinkai, M. Hashimoto, and T. Onoye, ``Future Prediction of Self-Heating in Short Intra-Block Wires,'' In Proc. International Symposium on Quality Electronic Design (ISQED), pp. 660-665, March 2007.
[77]  K. Shinkai, M. Hashimoto, A. Kurokawa, and T. Onoye, ``A Gate Delay Model Focusing on Current Fluctuation Over Wide-Range of Process and Environmental Variability,'' In Proc. International Conference on Computer-Aided Design (ICCAD), pp. 47-53, November 2006.
[78]  J. Ashida, R. Miyamoto, H. Tsutsui, T. Onoye, and Y. Nakamura, ``Probabilistic Pedestrian Tracking Based on a Skeleton Model,'' In Proc. International Conference on Image Processing, pp. 2825--2828, October 2006.
[79]  Y. Ogasahara, M. Hashimoto, and T. Onoye, ``Measurement of Inductive Coupling Effect on Timing in 90nm Global Interconnects,'' In Proc. IEEE Custom Integrated Circuits Conference, pp. 721--724, September 2006.
[80]  A. Kosaka and T. Onoye, ``Pipeline Processing of Continuous Speech Recognition Algorithm for Embedded System Implementation,'' In Proc. International Technical Conference on Circuits/Systems, Computers and Communication, vol. , pp. 373--376, July 2006.
[81]  F. Hyuga, T. Masuzaki, H. Tsutsui, T. Onoye, and Y. Nakamura, ``A JPEG Coding Scheme for High Fidelity Images by Halftoning Less Signification Extra Bits,'' In Proc. International Technical Conference on Circuits/Systems, Computers and Communication, vol. , pp. 97--100, July 2006.
[82]  T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, and M. Hashimoto, ``Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in Soc Design,'' In Proceedings of IEEE Wrokshop on Signal Propagation on Interconnects (SPI), pp. 227--230, May 2006.
[83]  K. Tsujino, W. Kobayashi, T. Onoye, and Y. Nakamura, ``Automated Design of Digital Filters for 3-D Sound Localization in Embedded Applications,'' In Proc. International Conf. Audio, Speech, and Signal Processing (ICASSP2006), p. V.349--V.352, May 2006.
[84]  K. Shinkai, M. Hashimoto, A. Kurokawa, and T. Onoye, ``A Gate Delay Model Focusing on Current Fluctuation Over Wide-Range of Process and Environmental Variability,'' In Proc. International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pp. 59-64, February 2006.
[85]  T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, and M. Hashimoto, ``Effective Si-Substrate Modeling for Frequency-Dependent Interconnect Resistance and Inductance Extraction,'' In The 3rd International Workshop on Compact Modeling, pp. 51--56, January 2006.
[86]  M. Hashimoto, A. Tsuchiya, A. Shinmyo, and H. Onodera, ``Performance Prediction of On-Chip High-Throughput Global Signaling,'' In Proceedings of IEEE 14th Topical Meeting on Electrical Performance of Electronic Packaging (EPEP), pp. 79-82, October 2005.
[87]  T. Matsumura, N. Iwanaga, T. Onoye, W. Kobayashi, I. Shirakawa, and I. Arungsrisangchai, ``3D Sound Movement System for Embedded Applications,'' In in Proc. IEEE International Symposium on Circuits and Systems (ISCAS2005), Kobe, Japan, pp. 5345-5348, May 2005.
[88]  R. Miyamoto, H. Sugita, Y. Hayashi, H. Tsutsui, T. Masuzaki, T. Onoye, and Y. Nakamura, ``High Quality Motion JPEG2000 Coding Scheme Based on the Human Visual System,'' In Proc. IEEE Int’l Symp. Circuits and Systems, pp. 2096--2099, May 2005.
[89]  A. Tsuchiya, M. Hashimoto, and H. Onodera, ``Substrate Loss of On-Chip Transmission-Lines with Power/Ground Wires in Lower Layer,'' In Proceedings of IEEE Workshop on Signal Propagation on Interconnects (SPI), Proceedings of IEEE Workshop on Signal Propagation on Interconnects (SPI), May 2005.
[90]  R. Miyamoto, Y. Hayashi, H. Tsutsui, T. Masuzaki, T. Onoye, and Y. Nakamura, ``Video Quality Enhancement for Motion JPEG2000 Encoding Based on the Human Visual System,'' In Proc. IEEE Asia Pacific Conference on Circuits and Systems, pp. 1161--1164, December 2004.
[91]  M. Hashimoto, A. Tsuchiya, A. Shinmyo, and H. Onodera, ``Performance Prediction of On-Chip Global Signaling,'' In IEEE Electrical Design of Advanced Packaging and Systems (EDAPS) , pp. 87-100, November 2004.
[92]  M. Hashimoto, A. Tsuchiya, and H. Onodera, ``On-Chip Global Signaling by Wave Pipelining,'' In IEEE 13th Topical Meeting on Electrical Performance of Electronic Packaging (EPEP), pp. 311-314, October 2004.
[93]  J. Ashida, R. Miyamoto, H. Tsutsui, T. Onoye, and Y. Nakamura, ``A Scalable Approach for Estimation of Focus of Expansion,'' In Proc. IASTED International Conference on Visualization, Imaging, and Image Processing, pp. 6--11, September 2004.
[94]  A. Tsuchiya, M. Hashimoto, and H. Onodera, ``Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling,'' In Proceedings of IEEE Custom Integrated Circuits Conference (CICC), pp. 489-492, September 2004.
[95]  A. Kotani, Y. Asai, Y. Nakamura, S. Okada, N. Koyama, K. Yamane, Y.Okano, Y. Mitsuyama, and T. Onoye, ``Visibility Font Technology on High Resolution Color LCD "LCFONT.c",'' In in Proc. The 2003 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2003), Kang-Woo Do, Korea, vol. 1, pp. 535--538, July 2003.
[96]  S. Komata, A. Pal, N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa, ``Interactive Interface of Realtime 3D Sound Movement for Embedded Applications,'' In in Proc. IEEE International Symposium on Circuits and Systems (ISCAS2003) , Bankok, Thailand, vol. II, pp. 520--523, May 2003.
[97]  S. Tani, Y. Uchida, M. Furuie, S. Tsukiyama, B. Lee, S. Nishi, Y. Kubota, I. Shirakawa, and S. Imai, ``A Parasitic Capacitance Modeling Method for Non-Planar Interconnects,'' In in Proc. the Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI 2003), pp. 294--299, April 2003.
[98]  T. Yuasa, Y. Soga, T. Izumi, T. Onoye, and Y. Nakamura, ``An Improved Communication Channel in Dynamic Reconfigurable Device for Multimedia Applications,'' In Proc. EUROMEDIA, pp. 152--157, April 2003.
[99]  S. Tani, Y. Uchida, M. Furuie, S. Tsukiyama, B. Lee, S. Nishi, Y. Kubota, I. Shirakawa, and S. Imai, ``Parasitic Capacitance Modeling for Multilevel Interconnects,'' In in Proc. IEEE Proceedings of Asia-Pacific Conference on Circuits and Systems 2002, vol. 1, pp. 59--64, December 2002.
[100]  A. Kosaka, S. Yamaguchi, H. Okuhata, T. Onoye, and I. Shirakawa, ``VLSI Implementation of Ogg Vorbis Decoder for Embedded Applications,'' In in Proc. 15th Annual IEEE International ASIC/SoC Conference(ASIC/SoC2002), Rochester, N.Y., pp. 20--24, September 2002.
[101]  M. H. Miki, M. Kimura, T. Onoye, and I. Shirakawa, ``High Performance Java Hardware Engine and Software Kernel for Embedded Systems,'' In in Proc. 11th IFIP International Conference on Very Large Scale Integration (VLSI-SOC 2001), Montpellier-Le Corum, France, pp. 365--369, December 2001.
[102]  N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa, ``DSP Implementaion of 3D Sound Localization Algorithm for Monaural Sound Source,'' In in Proc. The 8th IEEE International Conference on Electronics, Circuits and Systems(ICECS 2001), Malta, pp. 1061--1064, September 2001.
[103]  N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa, ``DSP Implementation of Low Computational 3D Sound Localization Algorithm,'' In in Proc. 200l IEEE Workshop on Signal Processing Systems, Design and Implementation(SIPS 2001), Antwerp, Belgium, pp. 109--116, September 2001.
[104]  N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa, ``DSP Implementation of Realtime 3D Sound Localization Algorithm,'' In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC '01), Tokushima, Japan, pp. 1140--1143, July 2001.
[105]  N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa, ``Low Power DSP Implementation of 3D Sound Localization for Monaural Sound Source,'' In in Proc. World Multiconference on Systemics, Cybernetics and Informatics (SCI 2001), Orlando, Florida, USA, pp. 173--177, July 2001.
[106]  Y. Mitsuyama, Z. Andales, T. Onoye, and I. Shirakawa, ``VLSI Architecture of Dynamically Reconfigurable Hardware-Based Cipher,'' In in Proc. IEEE International Symposium on Circuits and Systems (ISCAS2001) , Sydney, Australia, vol. IV, pp. 734--737, May 2001.
[107]  K. Kawamoto, S. Mizuno, H. Abe, Y. Higuchi, S. Fujino, and I. Shirakawa, ``A Shingle Chip Automotive Control LSI Using SOI BiCDMOS,'' In in Proc. of 2000 International Conference on Solid State Device and Materials, pp. 486-487, August 2000.
[108]  N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa, ``Low Power DSP Implementation of 3D Sound Localization,'' In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2000), Pusan, Korea, pp. 253--256, July 2000.
[109]  W. Kobayashi, N. Sakamoto, T. Onoye, and I. Shirakawa, ``3D Acoustic Image Localization Algorithm by Embedded DSP,'' In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2000), Pusan, Korea, pp. 264--267, July 2000.
[110]  T. Watanabe and N. Ishiura, ``Minimization of Spill Code Insertion by Register Constraint Analysis for Code Generation for Application Specific DSPs,'' In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2000), Pusan, Korea, pp. 953--956, July 2000.
[111]  N. Ishiura, T. Watanabe, and M. Yamaguchi, ``A Code Generation Method for Datapath Oriented Application Specific Processor Design,'' In in Proc. Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI 2000), pp. 71--78, April 2000.
[112]  M. Oshita, M. Tarui, T. Onoye, and I. Shirakawa, ``Pipelined Implementation of JBIG Arithmetic Coder,'' In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC '99), Sado, Japan, pp. 470--473, July 1999.
[113]  K. Asari, Y. Mitsuyama, T. Onoye, I. Shirakawa, H. Hirano, T. Honda, T. Otsuki, T. Baba, and T. Meng, ``Multi-Mode and Multi-Level Technologies for FeRAM Embedded Reconfigurable Hardware,'' In in Proc. IEEE Internatinal Solid-State Circuits Conference, pp. 106--107, February 1999.
[114]  H. Fujisima, Y. Takemoto, T. Yoneda, T. Onoye, and I. Shirakawa, ``Hybrid VLSI Architecture for Motion Compensation and Texture Mapping,'' In in Proc. IEEE International Workshop on Intelligent Signal Processing and Communication Systems, pp. 383--386, November 1998.
[115]  J. Fan, G. Fujita, M. Furuie, T. Onoye, and I. Shirakawa, ``Structual Objeco-Oriented Video Segmentation and Representation Algorithm,'' In in Proc. IEEE International Workshop on Intelligent Signal Processing and Communication Systems, pp. 78--82, November 1998.
[116]  H. Fujisima, Y. Takemoto, T. Onoye, I. Shirakawa, and K. Matsumura, ``Matrix-Vector Multiplier Module for Natural/Synthetic Hybrid Video Coding,'' In in Proc. IEEE Asia Pacific Conference on Circuits and Systems, pp. 631--634, November 1998.
[117]  K. Matsumura, G. Fujita, I. Shirakawa, and H. Inada, ``A Wireless Data System Constructed of SAW-Based Receiver/Transmitter and Its Applications to Medical Cares,'' In in Proc. IEEE Radio & Wireless Conf., pp. 47--50, August 1998.
[118]  K. Matsumura, G. Fujita, I. Shirakawa, and H. Inada, ``A Wireless Data System by Means of SAW-Based Transmitter/Receiver and Its Applications to Medical Cares,'' In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications, pp. 299--302, July 1998.
[119]  H. Fujisima, Y. Takemoto, T. Onoye, and I. Shirakawa, ``Matrix-Vector Multiplier for Natural/Synthetic Hybrid Video Coding,'' In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications, pp. 1269--1272, July 1998.
[120]  M. Yamaguchi, N. Ishiura, and T. Kambe, ``Binding and Scheduling Algorithms for Highly Retargetable Compilation,'' In in Proc. Aia and South Pacific Design Automation Conference (ASP-DAC '98), pp. 93-98, February 1998.
[121]  N. Ishiura and M. Yamaguchi, ``Instruction Code Compression for Application Specific VLIW Processors Based on Automatic Field Partitioning,'' In in Proc. of the Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI'97), pp. 105-109, December 1997.
[122]  H. Okuhata, H. Uno, K. Kumatani, I. Shirakawa, and T. Chiba, ``A 4Mbps Infrared Wireless Link Dedicated to Mobile Computing,'' In in Proc. IEEE International Performance, Computing, and Communications Conference, pp. 463-467, February 1997.
[123]  H. Uno, K. Kumatani, H. Okuhata, T. Masaki, I. Shirakawa, and T. Chiba, ``A 4Mbps Infrared Wireless Communication Link for Mobile Computing,'' In in Proc. Workshop on Multi-Dimensional Mobile Communications (MDMC '96), pp. 267-271, July 1996.
研究会等発表論文
[1]  藤原 健, 伊藤 雄一, 續 毅海, 高嶋 和樹, 尾上 孝雄, ``演奏者の重心移動を用いた演奏連携度と演奏に対する評価,'' HCGシンポジウム2016論文集, pp. 186-189, December 2016.
[2]  續 毅海, 伊藤 雄一, 藤原 健, 高嶋 和毅, 尾上 孝雄, ``演奏者の重心移動を用いた演奏連携度の取得に関する検討,'' ヒューマンインタフェース学会研究会研究報告集, vol. 18, no. 5, pp. 15-18, 2016.
[3]  E. Aliwarga, J. Yu, M. Hatanaka, and T. Onoye, ``Hardware Architecture of Generic Soft Cascaded Linear Svm Classifier,'' , no. 75, 電子情報通信学会ディペンダブルコンピューティング研究会, June 2015.
[4]  郡浦 宏明, 今川 隆司, 密山 幸男, 橋本 昌宜, 尾上 孝雄, ``動作合成に対応した信頼性可変混合粒度再構成可能アーキテクチャの検討,'' 信学技報, RECONF2013-8, vol. 113, no. 52, pp. 41-46, May 2013.
[5]  天木 健彦, 橋本 昌宜, 密山 幸男, 尾上 孝雄, ``確率的動作モデルを用いたオシレータベース真性乱数生成回路のワーストケース設計手法,'' 信学技報, VLD2012-154, vol. 112, no. 451, pp. 099-104, March 2013.
[6]  天木 健彦, 橋本 昌宜, 尾上 孝雄, ``ゆらぎ増幅回路を用いたオシレータベース物理乱数生成器,'' 信学技報, ICD2011-118, vol. 111, no. 352, pp. 087-092, December 2011.
[7]  郡浦 宏明, 密山 幸男, 橋本 昌宜, 尾上 孝雄, ``動的再構成可能アーキテクチャによる故障回避機構の定量的評価,'' 信学技報, RECONF2011-6, vol. 111, no. 31, pp. 31-36, May 2011.
[8]  天木 健彦, 橋本 昌宜, 密山 幸男, 尾上 孝雄, ``確率的動作モデルを用いたオシレータベース物理乱数生成器の設計手法,'' 情報処理学会研究報告, SLDM2010-147, vol. 2010-SLDM-147, no. 19, pp. 1-6, November 2010.
[9]  新開 健一, 橋本 昌宜, ``広範囲な製造・環境ばらつきに対応したゲート遅延モデル,'' 情報処理学会DAシンポジウム, pp. 73-78, August 2009.
[10]  郡浦 宏明, 密山 幸男, 橋本 昌宜, 尾上 孝雄, ``NBTI による劣化予測におけるトランジスタ動作確率算出法の評価,'' 情報処理学会DAシンポジウム, pp. 181-186, August 2009.
[11]  松下裕丈, 河村侑輝, 尾上孝雄, 大原一人, 芥子育雄, ``携帯機器における動画像ストリーム高速簡略復号の一手法,'' IEICE Technical Report SIS2009-4 (2009-6), pp. 19-24, June 2009.
[12]  濱本 浩一, 橋本 昌宜, 密山 幸男, 尾上 孝雄, ``レイアウトを考慮した基板バイアスクラスタリング手法,'' 信学技報, VLD2008-159 , vol. 108, no. 478, pp. 195-200, March 2009.
[13]  榎並 孝司, 橋本 昌宜, 佐藤 高史, ``電源ノイズ考慮統計的タイミング解析を用いたデカップリング容量割当手法,'' 信学技報, VLD2008-161, vol. 108, no. 478, pp. 207-212, March 2009.
[14]  更田 裕司, 橋本 昌宜, 密山 幸男, 尾上 孝雄, ``サブスレッショルド回路における基板バイアスを考慮したトランジスタのばらつきモデリングとリングオシレータを用いた検証,'' 信学技報, VLD2008-159, vol. 108, no. 478, pp. 201-206, March 2009.
[15]  橋本亮司, 筒井 弘, 尾上孝雄, 猪飼知宏, ``DCT領域 Distributed Video Coding における尤度推定手法,'' 信学技報, IE2008-209, vol. 108, no. 425, pp. 31-36, February 2009.
[16]  渡邊賢治, 達可敏充, 畠中理英, 尾上孝雄, ``屋内位置推定システムのための間取り推定に関する一検討,'' 信学技報, USN2008-33, vol. 108, no. 138, pp. 129-134, July 2008.
[17]  岡田 雅司, 岩永 信之, 松村 友哉, 尾上 孝雄, 小林 亙, ``ファジィクラスタリングに基づく多音源立体音像定位手法,'' 信学技報, SIS2008-1, vol. 108, no. 85, pp. 001-006, June 2008.
[18]  濱本 浩一, 更田 裕司, 橋本 昌宜, 密山 幸男, 尾上 孝雄, ``基板バイアス印加レイアウト方式の面積効率と速度制御性の評価,'' 信学技報, CAS2008-14, VLD2008-27, SIP2008-48(2008-6), pp. 75-79, June 2008.
[19]  小笠原泰弘, 橋本昌宜, 尾上孝雄, ``バス配線による誘導性クロストークノイズによる遅延変動の実測とノイズ重ねあわせ効果の検証,'' , 信学技報, VLD2007-153, March 2008.
[20]  二宮 進有, 橋本 昌宜, ``SSTAにおける空間的相関を持つ製造ばらつきのグリッドベースモデル化法の検討,'' 信学技報, VLD2007-91, DC2007-46, vol. 107, no. 336, pp. 13-17, November 2007.
[21]  阿部 慎也, 橋本 昌宜, 尾上 孝雄, ``製造ばらつきを考慮したメッシュ型クロック分配網のスキュー評価,'' 情報処理学会DAシンポジウム, pp. 133-138, August 2007.
[22]  小笠原 泰弘, 橋本 昌宜, 尾上 孝雄, ``90nm グローバル配線における誘導性クロストークノイズによる遅延変動の実測,'' 信学技報, CPM2006-131, ICD2006-173, pp. 13--18, January 2007.
[23]  吉田 明弘, 松村 友哉, 岩永 信之, 小林 亙, 尾上 孝雄, ``頭部近傍における立体音像定位の向上に関する一手法,'' 日本音響学会聴覚研究会資料, H-2006-134, December 2006.
[24]  榎並 孝司, 橋本 昌宜, 尾上 孝雄, ``主成分分析による電源電圧変動の統計的モデル化手法,'' 情報処理学会DAシンポジウム, pp. 205--210, July 2006.
[25]  新開 健一, 橋本 昌宜, 黒川 敦, 尾上孝雄, ``電流変動に着目した広範囲な製造・環境ばらつき対応ゲート遅延モデル,'' 第19回 回路とシステム軽井沢ワークショップ, pp. 559-564, April 2006.
[26]  小谷 章夫, 種村 嘉高, 朝井 宣美, 中村 安久, 大塚 正章, 密山 幸男, 尾上 孝雄, ``文字重心位置評価手法とその可読性評価への応用,'' 信学技報, SIS2005-23, pp. 1--6, September 2005.
[27]  吉田 明弘, 松村 友哉, 岩永 信之, 小林 亙, 尾上 孝雄, ``近距離音像の定位を実現するための頭部伝達関数の特徴解析,'' 信学技報, EA2005-39, pp. 29--34, August 2005.
[28]  中川陽介, 岩永信之, 小林亙, 古谷一彦, 尾上孝雄, 白川功, ``周波数特性除去に基づくスピーカによるバイノーラル再生,'' 聴覚研究会, pp. 17--22, January 2004.
[29]  阪本 憲成, 小林 亙, 尾上 孝雄, 白川 功, ``3 次元音像定位リアルタイムアルゴリズムの DSP 実装とその評価,'' 信学技報, CAS2001-50, pp. 147--154, June 2001.
[30]  阪本 憲成, 小林 亙, 尾上 孝雄, 白川 功, ``モノラル音の実時間 3 次元音像定位アルゴリズムの 1 チップ DSP 実装,'' 信学会 第 15 回ディジタル信号処理シンポジウム C6-2, pp. 599--604, November 2000.
[31]  渡辺 辰雄, 石浦 菜岐佐, ``特定用途向け DSP 用リターゲッタブルコンパイラによるデータパス指向協調設計手法,'' 信学技報, VLD2000-89, pp. 119--124, November 2000.
[32]  小林 亙, 阪本 憲成, 尾上 孝雄, 白川 功, ``3 次元音像定位リアルタイムアルゴリズムとその低消費電力 DSP 実装,'' 信学技報, CAS2000-13, pp. 97--102, June 2000.
[33]  渡辺 辰雄, 石浦 菜岐佐, 山口 雅之, ``特定用途向け DSP のデータパス指向協調設計におけるコード生成手法,'' 信学会 第13回回路とシステム(軽井沢)ワークショップ, pp. 539--544, April 2000.
[34]  渡辺 辰雄, 石浦 菜岐佐, 山口 雅之, ``非直交なデータパスに対するリターゲッタブルコンパイラのスケジューリング手法,'' 信学会 第12回回路とシステム軽井沢ワークショップ, pp. 109--114, April 1999.
[35]  長尾明, 澤卓, 磯部雅哉, 神戸尚志, 白川功, ``マイクロ波集積回路向きレイアウト設計に対する自動化手法,'' 電子情報通信学会第10回回路とシステム軽井沢ワークショップ, pp. 433-438, April 1997.
大会等発表論文
[1]  岡田 雅司, 畠中 理英, 尾上 孝雄, ``秘匿化機能の分散化に基づくセキュアなアンビエント無線通信システムの実装,'' 第14回 DSPS教育会議 予稿集, pp. 71-72, September 2012.
[2]  岡田 雅司, 尾上 孝雄, 小林 亙, ``GPU レイトレーサと多音源音像定位手法を用いた対話的な三次元音場生成システム,'' 電子情報通信学会総合大会, A-20-7, March 2012.
[3]  更田 裕司, 橋本 昌宜, 密山 幸男, 尾上 孝雄, ``加算器を用いたsubthreshold 回路の設計指針の検討,'' 電子情報通信学会総合大会, A-3-17, March 2007.
[4]  中川 克哉, 川北 将, 尾上孝雄, 千葉 徹, 白川 功, ``適合的情報空間連係の利便性の考察,'' 情報処理学会 第2回 情報科学技術フォーラム(FIT2003), vol. 4, pp. 267--268, September 2003.
[5]  阪本 憲成, 小林 亙, 尾上 孝雄, 白川 功, ``モノラル音 3 次元音像定位処理システムのハードウェア実装,'' 信学会 ソサイエティ大会, A-4-40, September 2001.
[6]  Gulistan Raja, 宋 天, 藤田 玄, 尾上 孝雄, 白川 功, ``H.263 向きデブロッキングフィルタおよび拡張 Intra 符号化処理の VLSI 化設計,'' 信学会 総合大会, A-3-7, March 2001.
[7]  小俣 真也, 小林 亙, 阪本 憲成, 尾上 孝雄, 白川 功, ``汎用 DSP 実装用 3 次元音像定位リアルタイムアルゴリズム,'' 映像情報メディア学会 冬季大会, 1-11, December 2000.
[8]  渡辺 辰雄, 石浦 菜岐佐, ``特定用途向け DSP のコード生成におけるスピルコードの最小化,'' 信学会 ソサイエティ大会, A-3-20, October 2000.
[9]  小林 亙, 阪本 憲成, 尾上 孝雄, 白川 功, ``3 次元音像定位のための実時間アルゴリズム,'' 信学会 ソサイエティ大会, A-4-23, October 2000.
[10]  竹本 裕介, 藤嶋 秀幸, 尾上 孝雄, 白川 功, ``画像符号化と3次元CGで共用可能な行列・ベクトル乗算器,'' 信学会 総合大会, C-12-19, May 1998.

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