論文誌
[1]  Z. Andales, Y. Mitsuyama, T. Onoye, and I. Shirakawa, ``A Novel Dynamically Reconfigurable Hardware-Based Cipher,'' 情報処理学会論文誌, vol. 42, no. 4, pp. 958--966, April 2001.
国際会議
[1]  Y. Mitsuyama, Z. Andales, T. Onoye, and I. Shirakawa, ``Burst Mode: a New Acceleration Mode for 128-Bit Block Ciphers,'' In in Proc. IEEE 24th Custom Integrated Circuits Conference (CICC2002), Orland, Florida, pp. 151--154, May 2002.
[2]  Y. Mitsuyama, Z. Andales, T. Onoye, I. Shirakawa, and I. Arungsrisangchai, ``VLSI Architecture of Burst Mode Acceleration for 128-Bit Block Ciphers,'' In ibid, vol. II, pp. 344--347, May 2002.
[3]  Z. Andales, Y. Mitsuyama, T. Onoye, and I. Shirakawa, ``System Performance Evaluation of High-Speed Burst Mode for 128-Bit Block Ciphers,'' In in Proc. Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI 2001), Nara, Japan, pp. 332--339, October 2001.
[4]  Y. Mitsuyama, Z. Andales, T. Onoye, and I. Shirakawa, ``VLSI Implementation of High Performance Burst Mode for 128-Bit Block Ciphers,'' In in Proc. 14th Annual IEEE International ASIC/SoC Conference (ASIC/SoC2001), Washington, D.C., pp. W.1.1.1--W.1.1.5, September 2001.
[5]  Y. Mitsuyama, Z. Andales, T. Onoye, and I. Shirakawa, ``VLSI Architecture of Dynamically Reconfigurable Hardware-Based Cipher,'' In in Proc. IEEE International Symposium on Circuits and Systems (ISCAS2001) , Sydney, Australia, vol. IV, pp. 734--737, May 2001.
[6]  Z. Andales, Y. Mitsuyama, T. Onoye, and I. Shirakawa, ``A High Performance Burst Mode Approach for 128-Bit Block Ciphers,'' In in Proc. EUROMEDIA2001, Valencia, Spain, pp. 146--150, April 2001.
[7]  Y. Mitsuyama, Z. Andales, T. Onoye, and I. Shirakawa, ``A Dynamically Reconfigurable Hardware-Based Cipher Chip,'' In in Proc. Asia and South Pacific Design Automation Conference (ASP-DAC 2001), Yokohama, Japan, pp. 11--12, January 2001.
[8]  Y. Mitsuyama, Z. Andales, T. Onoye, and I. Shirakawa, ``VLSI Implementation of Dynamically Reconfigurable Hardware-Based Cryptosystem,'' In in Symposium on VLSI Circuits Digest of Technical Papers, Hawaii, USA, pp. 204--205, June 2000.
[9]  Z. Andales, Y. Mitsuyama, T. Onoye, and I. Shirakawa, ``Chameleon: a Dynamically Reconfigurable Hardware-Based Cryptosystem,'' In in Proc. EUROMEDIA2000 , Antwerp, Belgium, pp. 90--94, May 2000.
研究会等発表論文
[1]  密山 幸男, Zaldy Andales, 尾上 孝雄, 白川 功, ``ブロック暗号の高速化暗号モードとその VLSI 化設計,'' 信学技報, CAS2001-41, pp. 89--94, June 2001.
[2]  Y. Mitsuyama, Z. Andales, T. Onoye, and I. Shirakawa, ``A New Approach for 128-Bit Block Ciphers,'' In 信学会 第14回回路とシステム(軽井沢)ワークショップ, pp. 231--236, April 2001.
[3]  密山 幸男, Zaldy Andales, 尾上 孝雄, 白川 功, ``リコンフィギュラブルロジックを用いたハードウェア向き暗号方式,'' 信学会 第13回回路とシステム(軽井沢)ワークショップ, pp. 367--372, April 2000.
[4]  Zaldy ANDALES, 密山 幸男, 浅利 康二, 尾上 孝雄, 白川 功, ``リコンフィグラブルハードウェアを用いた暗号システム,'' 信学技報, CAS99-63, NLP99-87, pp. 7--14, September 1999.
大会等発表論文
[1]  密山 幸男, Zaldy Andales, 尾上 孝雄, 白川 功, ``リコンフィギュラブルロジックを用いた暗号方式,'' 信学会 ソサイエティ大会, A-4-42, October 2000.

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