論文誌
[1]  B.Y. Song, M. Furuie, Y. Yoshida, T. Onoye, and I. Shirakawa, ``Low-Power VLSI Implementation by NMOS 4-Phase Dynamic Logic,'' Trans. of IPSJ, vol. 41, no. 4, pp. 899--907, April 2000.
[2]  B.Y. Song, M. Furuie, Y. Yoshida, T. Onoye, and I. Shirakawa, ``Low-Power Scheme of NMOS 4-Phase Dynamic Logic,'' IEICE Trans. Electron., vol. E82--C, no. 9, pp. 1772--1776, September 1999.
[3]  吉田 幸弘, 宋 宝玉, 奥畑 宏之, 尾上 孝雄, 白川 功, ``組み込み用プロセッサの低消費電力化に関する一手法,'' 電子情報通信学会論文誌, vol. J80-A, no. 5, pp. 765-771, May 1997.
国際会議
[1]  M. Furuie, B. Y. Song, Y. Yoshida, T. Onoye, and I. Shirakawa, ``Layout Generation of Array Cell for NMOS 4-Phase Dynamil Logic,'' In in Proc. ASP-DAC2000, pp. 529--532, January 2000.
[2]  M. Furuie, B. Y. Song, Y. Yoshida, T. Onoye, and I. Shirakawa, ``Layout Generation for Low-Power NMOS 4-Phase Dynamic Logic Array,'' In in Proc. IEEE Region 10 Conference (TENCON '99), pp. 872--875, September 1999.
[3]  B. Y. Song, M. Furuie, Y. Yoshida, T. Onoye, and I. Shirakawa, ``Array Macro Cell Architecture for Low-Power NMOS 4-Phase Dynamic Logic,'' In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC '99), Sado, Japan, pp. 561--564, July 1999.
[4]  B.Y. Song, Y. Yoshida, T. Onoye, and I. Shirakawa, ``Low-Power Implementation by a New Logic Scheme of NMOS 4-Phase Dynamic Logic,'' In in Proc. Workshop on Synthesis and System Integration of Mixed Technologies, pp. 235--240, October 1998.
[5]  B.Y. Song, Y. Yoshida, T. Onoye, and I. Shirakawa, ``Delay and Power Simulation for a New Logic Scheme of NMOS 4-Phase Dynamic Logic,'' In in Proc. European Simulation Symposium, pp. 339--343, October 1998.
[6]  Y. Yoshida, B. Y. Song, H. Okuhata, T. Onoye, and I. Shirakawa, ``An Object Code Compression Approach to Embedded Processors,'' In in Proc. International Symposium on Low Power Electronics and Design, pp. 265-268, August 1997.
[7]  Y. Yoshida, B. Y. Song, H. Okuhata, T. Onoye, and I. Shirakawa, ``Low-Power Consumption Architecture for Embedded Processor,'' In in Proc. 2nd International Conference on ASIC, pp. 77-80, October 1996.
研究会等発表論文
[1]  古家 眞, 宋 宝玉, 吉田 幸弘, 尾上 孝雄, 白川 功, ``4相NMOSダイナミックロジック用アレイセル,'' 信学技報, CAS99-62, pp. 1--6, September 1999.
大会等発表論文
[1]  吉田幸宏, 宋宝玉, 奥畑宏之, 尾上孝雄, 白川功, ``組み込み用プロセッサの低消費電力化に対する一手法,'' 電子情報 通信学会ソサイアティ大会, SA-1-2, September 1996.

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