論文誌
[1]  長尾 明, 澤 卓, 重弘 裕二, 白川 功, 神戸 尚志, ``方形パッキング法の一算法,'' 電子情報通信学会論文誌, vol. J81-A, no. 10, pp. 1362--1371, October 1998.
[2]  I. Arungsrisangchai, Y. Shigehiro, I. Shirakawa, and H. Takahashi, ``A Fast Minimum Cost Flow Algorithm for Regenerating Optimal Layout of Functional Cells,'' IEICE Trans. Fundamentals of Electronics,Communications and Computer Sciences, vol. E80-A, no. 12, pp. 2589-2599, December 1997.
[3]  Y. Shigehiro, T. Nagata, I. Shirakawa, I. Arungsrisangchai, and H. Takahashi, ``Automatic Layout Recycling Based on Layout Description and Linear Programming,'' in Proc. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 15, no. 8, pp. 959-967, August 1996.
国際会議
[1]  I. Arungsrisangchai, Y. Shigehiro, I. Shirakawa, and H. Takahashi, ``A Fast Minimun Cost Flow Algofithm for VLSI Layout Compaction,'' In in Proc. IEEE International Symposium on Circuits and Systems, pp. 1672-1675, June 1997.
[2]  Y. Shigehiro, I. Shirakawa, I. Arungsrisangchai, and H. Takahashi, ``A Fast Minimum Cost Flow Algorithm and Its Application to VLSI Layout Compaction,'' In in Proc. Int'l Technical Conference on Circuits/Systems, Computers and Communications, pp. 951-954, July 1996.
[3]  K. Itoh, Y. Shigehiro, I. Shirakawa, and K. Matsumura, ``An Approach for Multi-Layer Gridless Routing,'' In in Proc. Printed Circuit World Convention VII, pp.P2-1-P2-7, May 1996.

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