論文誌
[1]  Y. Ogasahara, T. Enami, M. Hashimoto, T. Sato, and T. Onoye, ``Validation of a Full-Chip Simulation Model for Supply Noise and Delay Dependence on Average Voltage Drop with On-Chip Delay Measurement,'' IEEE Trans. on Circuits and Systems—II: Express Briefs, vol. 54, no. 10, pp. 868-872, October 2007.
国際会議
[1]  T. Enami, M. Hashimoto, and T. Sato, ``Decoupling Capacitance Allocation for Timing with Statistical Noise Model and Timing Analysis,'' In Proc. IEEE/ACM International Conference on Computer-Aided Design, pp. 420-425, November 2008.
[2]  Y. Ogasahara, T. Enami, M. Hashimoto, T. Sato, and T. Onoye, ``Measurement Results of Delay Degradation Due to Power Supply Noise Well Correlated with Full-Chip Simulation,'' In Proc.~IEEE Custom Integrated Circuits Conference, pp. 861--864, September 2006.
研究会等発表論文
[1]  榎並 孝司, 橋本 昌宜, 佐藤 高史, ``電源ノイズ考慮統計的タイミング解析を用いたデカップリング容量割当手法,'' 信学技報, VLD2008-161, vol. 108, no. 478, pp. 207-212, March 2009.
[2]  小笠原 泰弘, 榎並 孝司, 橋本 昌宜, 佐藤 高史, 尾上 孝雄, ``電源ノイズによる遅延変動の測定と電源ノイズを再現するフルチップシミュレーション手法,'' 信学技報, CPM2006-132, ICD2006-174, pp. 19--23, January 2007.

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