論文誌
[1]  T. Watanabe and N. Ishiura, ``Resister Constraint Analysis to Minimize Spill Code for Application Specific DSPs,'' IEICE Trans. Fundamentals of Electronics Communications and Computer Sciences, vol. E84-A, no. 6, pp. 1541--1544, June 2001.
[2]  M. Takahashi, N. Ishiura, A. Yamada, and T. Kambe, ``Thread Composition Method for Hardware Compiler Bach Maximizing Resource Sharing among Processes,'' IEICE Trans. Fundamentals, vol. E83-A, no. 12, pp. 2456--2463, December 2000.
[3]  Masayuki Yamaguchi, Nagisa Ishiura, and Takashi Kambe, ``A Binding Algorithm for Retargetable Compilation to Non-Orthogonal DSP Architecture,'' IEICE Trans. Fundamentals, vol. E81-A, no. 12, pp. 2630--2639, December 1998.
[4]  M. Yamaguchi, A. Yamada, T. Nakaoka, T. Kambe, and N. Ishiura, ``Architecture Evaluation Based on the Datapath Structure and Parallel Constraint,'' IEICE Trans. Fundamentals of Electronics,Communications and Computer Sciences, vol. E80-A, no. 10, pp. 1853-1860, October 1997.
[5]  S. Yano and N. Ishiura, ``Embedded Memory Array Testing Using a Scannable Configuration,'' IEICE Trans.\ Fundamentals of Electronics,Communications and Computer Sciences, vol. E80-A, no. 10, pp. 1934-1944, October 1997.
[6]  S. Yano, K. Akagi, H. Inohara, and N. Ishiura, ``Application of Full Scan Design to Embedded Memory Arrays,'' in Proc. IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, vol. E80-A, no. 3, March 1997.
[7]  矢野政顕, 石浦菜岐佐, ``メモリアレーを含む順序回路へのスキャンパス 方式適用,'' 電子情報通信学会論文誌, vol. J79-D-I, no. 12, pp. 1055-1062, December 1996.
国際会議
[1]  T. Watanabe and N. Ishiura, ``Minimization of Spill Code Insertion by Register Constraint Analysis for Code Generation for Application Specific DSPs,'' In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2000), Pusan, Korea, pp. 953--956, July 2000.
[2]  N. Ishiura, T. Watanabe, and M. Yamaguchi, ``A Code Generation Method for Datapath Oriented Application Specific Processor Design,'' In in Proc. Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI 2000), pp. 71--78, April 2000.
[3]  M. Takahashi, N. Ishiura, A. Yamada, and T. Kambe, ``Thread Partitioning Method for Hardware Compiler Bach,'' In in Proc.\ Asia and South Pacific Design Automation Conference (ASP-DAC 2000), pp. 303--308, January 2000.
[4]  N. Ishiura and M. Yamaguchi, ``Operation Binding for Retargetable Compilers Minimizing Clock Cycles,'' In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC '99), Sado, Japan, pp. 705--708, July 1999.
[5]  N. Ishiura, M. Yamaguchi, and T. Kambe, ``A Graph-Based Algorithm of Operation Binding for Compilers Targeting Heterogeneous Datapath,'' In in Proc. IEEE Asia Pacific Conference on Circuits and Systems, pp. 395--398, November 1998.
[6]  J. Fan, G. Fujita, J. Yu, K. Miyanohana, T. Onoye, N. Ishiura, L. Wu, and I. Shirakawa, ``Hierarchical Object-Oriented Image and Video Segmentation Algorithm Based on 2D Entropic Thresholding,'' In in Proc. Electronic Imaging and Multimedia Systems II, SPIE, pp. 141--151, September 1998.
[7]  N. Ishiura, M. Yamaguchi, and N. Nitta, ``Field Partitioning Algorithms for Compression of Instruction Codes of Application Specific VLIW Processors,'' In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications, pp. 1387--1390, July 1998.
[8]  M. Yamaguchi, N. Ishiura, and T. Kambe, ``A Binding Algorithm for Retargetable Compilation to Non-Orthogonal Datapath Architectures,'' In in Proc. International Symposium on Circuits and Systems, WPA4-4, June 1998.
[9]  M. Yamaguchi, N. Ishiura, and T. Kambe, ``Binding and Scheduling Algorithms for Highly Retargetable Compilation,'' In in Proc. Aia and South Pacific Design Automation Conference (ASP-DAC '98), pp. 93-98, February 1998.
[10]  N. Ishiura and M. Yamaguchi, ``Instruction Code Compression for Application Specific VLIW Processors Based on Automatic Field Partitioning,'' In in Proc. of the Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI'97), pp. 105-109, December 1997.
[11]  S. Nakamura, N. Ishiura, T. Yamamoto, and I. Shirakawa, ``High-Level Synthesis System for Behavioral Descriptions with Conditional Branches,'' In in Proc. Int'l Technical Conference on Circuits/Systems, Computers and Communications, pp. 935-938, July 1996.
研究会等発表論文
[1]  渡辺 辰雄, 石浦 菜岐佐, ``特定用途向け DSP 用リターゲッタブルコンパイラによるデータパス指向協調設計手法,'' 信学技報, VLD2000-89, pp. 119--124, November 2000.
[2]  渡辺 辰雄, 石浦 菜岐佐, 山口 雅之, ``特定用途向け DSP のデータパス指向協調設計におけるコード生成手法,'' 信学会 第13回回路とシステム(軽井沢)ワークショップ, pp. 539--544, April 2000.
[3]  高橋 瑞樹, 石浦 菜岐佐, 山田 晃久, 神戸 尚志, ``ハードウェアコンパイラBachにおけるスレッド分割手法,'' 信学会 第12回回路とシステム(軽井沢)ワークショップ, pp. 103--108, April 1999.
[4]  渡辺 辰雄, 石浦 菜岐佐, 山口 雅之, ``非直交なデータパスに対するリターゲッタブルコンパイラのスケジューリング手法,'' 信学会 第12回回路とシステム軽井沢ワークショップ, pp. 109--114, April 1999.
[5]  服部 靖史, 石浦 菜岐佐, 山口 雅之, ``DSP向けリターゲッタブルコンパイラの演算器/転送経路のバインディング手法,'' 信学技報, VLD98-125, vol. 98, no. 447, pp. 55-61, December 1998.
[6]  山口雅之, 石浦菜岐佐, 神戸尚志, ``非直交なデータパスに対するリターゲッタブルコンパイラのバインディング手法,'' 信学会 第11回回路とシステム軽井沢ワークショップ, pp. 481--486, April 1998.
[7]  山口雅之, 石浦菜岐佐, 神戸尚志, ``組込み式システム向けリターゲッタブルコンパイラの方式,'' 電子情報通信学会技術研究報告, VLD97-90, FTS97-53, pp. 85-92, October 1997.
[8]  山本哲三朗, 石浦菜岐佐, 山口雅之, 服部靖史, ``組込みシステム向け高位合成システム,'' 電子情報通信学会技術研究報告, VLD97-91, FTS97-54, pp. 93-99, October 1997.
[9]  矢野政顕, 石浦菜岐佐, ``スキャンパス構成を利用した内蔵メモリの試験,'' 電子情報通信学会第10回回路とシステム軽井沢ワークショップ, pp. 95-100, April 1997.
[10]  S. Yano, K. Akagi, and N. Ishiura, ``A New Scan Path Approach to Memory Array Testing,'' In 電子情報通信学会第9回回路とシステム軽 井沢ワークショップ, pp. 55-60, April 1996.
大会等発表論文
[1]  渡辺 辰雄, 石浦 菜岐佐, ``特定用途向け DSP のコード生成におけるスピルコードの最小化,'' 信学会 ソサイエティ大会, A-3-20, October 2000.
[2]  石浦菜岐佐, 山口雅之, ``特定用途向けVLIW型プロセッサの命令コード圧縮手法,'' 電子情報通信学会ソサイエィ大会, A-3-10, August 1997.

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