論文誌
[1]  T. Amaki, M. Hashimoto, and T. Onoye, ``Jitter Amplifier for Oscillator-Based True Random Number Generator,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E96-A, no. 3, pp. 684--696, March 2013.
[2]  H. Konoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Stress Probability Computation for Estimating NBTI-Induced Delay Degradation,'' IEICE Trans. Fundamentals, vol. E94-A, no. 12, pp. 2545-2553, December 2011.
[3]  T. Enami, S. Ninomiya, K. Shinkai, S. Abe, and M. Hashimoto, ``Statistical Timing Analysis Considering Clock Jitter and Skew Due to Power Supply Noise and Process Variation,'' IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, vol. 93-A, no. 12, pp. 2399-2408, December 2010.
[4]  R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Measurement Circuits for Acquiring SET Pulse Width Distribution with Sub-FO1-Inverter-Delay Resolution,'' IEICE Transaction on Fundamentals of Electronics, Communications and Computer Sciences, vol. E93-A, no. 12, pp. 2417-2423, December 2010.
[5]  密山 幸男, 高橋 一真, 今井 林太郎, 橋本 昌宜, 尾上 孝雄, 白川 功, ``メディア処理向け再構成可能アーキテクチャでの動画像復号処理の実現,'' 電子情報通信学会論文誌, vol. J93-A, no. 6, pp. 397-413, June 2010.
[6]  K. Shinkai, M. Hashimoto, and T. Onoye, ``Prediction of Self-Heating in Short Intra-Block Wires,'' IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, vol. E93-A, no. 3, pp. 583-594, March 2010.
[7]  H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction,'' IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, vol. E92-A, no. 12, pp. 3094-3102, December 2009.
[8]  T. Enami, S. Ninomiya, and M. Hashimoto, ``Statistical Timing Analysis Considering Spatially and Temporally Correlated Dynamic Power Supply Noise,'' IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 4, pp. 541-553, April 2009.
[9]  K. Hamamoto, H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``An Experimental Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability,'' IEICE Trans. on Electronics, vol. E92-C, no. 2, pp. 281-285, February 2009.
[10]  Y. Mitsuyama, K. Takahashi, R. Imai, M. Hashimoto, T. Onoye, I. Shirakawa, ``Area-Efficient Reconfigurable Architecture for Media Processin,'' IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, vol. E91-A, no. 12, pp. 3651-3662, December 2008.
[11]  Y. Ogasahara, M. Hashimoto, and T. Onoye, ``Measurement and Analysis of Inductive Coupling Noise in 90nm Global Interconnects,'' IEEE Journal of Solid-State Circuits, vol. 43, no. 3, pp. 718-728, March 2008.
[12]  Y. Ogasahara, T. Enami, M. Hashimoto, T. Sato, and T. Onoye, ``Validation of a Full-Chip Simulation Model for Supply Noise and Delay Dependence on Average Voltage Drop with On-Chip Delay Measurement,'' IEEE Trans. on Circuits and Systems—II: Express Briefs, vol. 54, no. 10, pp. 868-872, October 2007.
[13]  Y. Ogasahara, M. Hashimoto, and T. Onoye, ``Quantitative Prediction of On-Chip Capacitive and Inductive Crosstalk Noise and Tradeoff between Wire Cross Sectional Area and Inductive Crosstalk Effect,'' In IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E90-A, no. 4, pp. 724--731, April 2007.
[14]  S. Takahashi, S. Tsukiyama, M. Hashimoto, and I. Shirakawa, ``A Sampling Switch Design Procedure for Active Matrix Liquid Crystal Displays,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E89-A, no. 12, pp. 3538--3545, December 2006.
[15]  S. Takahashi, S. Tsukiyama, M. Hashimoto, and I. Shirakawa, ``A Sampling Switch Design Procedure for Active Matrix Liquid Crystal Displays,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E89-A, no. 12, pp. 3538-3545, December 2006.
[16]  T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, and M. Hashimoto, ``Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in Soc Design,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E89-A, no. 12, pp. 3560-3568, December 2006.
[17]  内田好弘, 谷貞宏, 橋本昌宜, 築山修治, 白川功, ``グラウンド平面・シールド配線によるシステム・オン・パネルの配線間容量の低減と容量見積りの容易化,'' 情報処理学会論文誌, vol. 47, no. 6, pp. 1665--1673, June 2006.
[18]  内田 好弘, 谷 貞宏, 橋本 昌宜, 築山 修治, 白川 功, ``システム液晶のための配線容量抽出手法,'' 情報処理学会論文誌, vol. 46, no. 6, pp. 1395--1403, June 2005.
国際会議
[1]  Ryo Shirai, Tetsuya Hirose, and Masanori Hashimoto, ``Dedicated Antenna Less Power Efficient Ook Transmitter for Mm-Cubic Iot Nodes,'' Proceedings of European Microwave Conference (EuMC), (to appear).
[2]  Ryo Shirai, Jin Kono, Tetsuya Hirose, and Masanori Hashimoto, ``Near-Field Dual-Use Antenna for Magnetic-Field Based Communication and Electrical-Field Based Distance Sensing in Mm^3-Class Sensor Node,'' Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), pp. 124--127, May 2017.
[3]  Y. Masuda, M. Hashimoto, and T. Onoye, ``Measurement of Timing Error Detection Performance of Software-Based Error Detection Mechanisms and Its Correlation with Simulation,'' In ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pp. 28-35, March 2016.
[4]  Y. Masuda, M. Hashimoto, and T. Onoye, ``Performance Evaluation of Software-Based Error Detection Mechanisms for Localizing Electrical Timing Failures under Dynamic Supply Noise,'' In Proceedings of International Conference on Computer-Aided Design (ICCAD), pp. 315-322, November 2015.
[5]  S. Iizuka, Y. Masuda, M. Hashimoto, and T. Onoye, ``Stochastic Timing Error Rate Estimation under Process and Temporal Variations,'' In Proceedings of International Test Conference (ITC), October 2015.
[6]  Hiroaki Konoura, Dawood Alnajjar, Yukio Mitsuyama, Hiroyuki Ochi, Takashi Imagawa, Shinichi Noda, Kazutoshi Wakabayashi, Masanori Hashimoto, and Takao Onoye, ``Mixed-Grained Reconfigurable Architecture Supporting Flexible Reliability and C-Based Design,'' In ReConFig, December 2013.
[7]  S. Iizuka, M. Mizuno, D. Kuroda, M. Hashimoto, and T. Onoye, ``Stochastic Error Rate Estimation for Adaptive Speed Control with Field Delay Testing,'' In Proc. International Conference on Computer-Aided Design (ICCAD), pp. 107-114, November 2013. (San Jose)
[8]  Jin Kono, Masanori Hashimoto, Takao Onoye, ``Feasibility Evaluation of Near-Field Communication in Clay with 1-Mm3 Antenna,'' Microwave Conference Proceedings (APMC), 2013 Asia-Pacific, pp. 1121-1123, 2013.
[9]  H. Konoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Implications of Reliability Enhancement Achieved by Fault Avoidance on Dynamically Reconfigurable Architectures,'' In Proc. 21st International Conference on Field Programmable Logic and Applications (FPL2011), Chania, Crete, Greece, pp. 189-194, September 2011.
[10]  Toshihiro Kameda, Hiroaki Konoura, Yukio Mitsuyama, Masanori Hashimoto, and Takao Onoye, ``Nbti Mitigation by Giving Random Scan-In Vectors during Standby Mode,'' In PATMOS2011, September 2011.
[11]  T. Amaki, M. Hashimoto, and T. Onoye, ``An Oscillator-Based True Random Number Generator with Jitter Amplifier,'' In Proc. IEEE International Symposium on Circuits and Systems (ISCAS 2011), pp. 725-728, May 2011.
[12]  R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Neutron Induced Single Event Multiple Transients with Voltage Scaling and Body Biasing,'' In Proc. International Reliability Physics Symposium (IRPS), April 2011.
[13]  T. Amaki, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``A Design Procedure for Oscillator-Based Hardware Random Number Generator with Stochastic Behavior Modeling,'' In Proc. International Workshop on Information Security Applications (WISA 2010), pp. 107-121, January 2011.
[14]  T. Amaki, M. Hashimoto, and T. Onoye, ``Jitter Amplifier for Oscillator-Based True Random Number Generator,'' In Proc. Asia and South Pacific Design Automation Conference (ASP-DAC 2011), pp. 81-82, January 2011.
[15]  K. Shinkai and M. Hashimoto, ``Device-Parameter Estimation with On-Chip Variation Sensors Considering Random Variability,'' In Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 683-688, January 2011.
[16]  K. Shinkai and M. Hashimoto, ``Self-Heating in Nano-Scale Vlsi Interconnects,'' In Proceedings of International Workshop on Information Communication Technology (ICT), pp. S-1-6, August 2010.
[17]  S. Abe, K. Shinkai, M. Hashimoto, and T. Onoye, ``Clock Skew Reduction by Self-Compensating Manufacturing Variability with On-Chip Sensors,'' In Proc. Great Lakes Symposium on VLSI (GLSVLSI), May 2010.
[18]  H. Konoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Comparative Study on Delay Degrading Estimation Due to Nbti with Circuit/Instance/Transistor-Level Stress Probability Consideration,'' In Proc. International Symposium on Quality Electronic Design (ISQED), pp. 646-651, March 2010.
[19]  R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye, ``Measurement Circuits for Acquiring SET Pulse Width Distribution with Sub-FO1-Inverter-Delay Resolution,'' In Proc. International Symposium on Quality Electronic Design (ISQED), March 2010.
[20]  T. Enami, S. Ninomiya, K. Shinkai, S. Abe, and M. Hashimoto, ``Statistical Timing Analysis Considering Clock Jitter and Skew Due to Power Supply Noise and Process Variation,'' In Proc. International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pp. 41-46, March 2010.
[21]  S. Abe, K. Shinkai, M. Hashimoto, and T. Onoye, ``Clock Skew Reduction by Self-Compensating Manufacturing Variability with On-Chip Sensors,'' In Proc. International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), March 2010.
[22]  H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``Adaptive Performance Control with Embedded Timing Error Predictive Sensors for Subthreshold Circuits,'' In Proc. Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 361-362, January 2010.
[23]  H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``Adaptive Performance Compensation with In-Situ Timing Error Prediction for Subthreshold Circuits,'' In Proc. IEEE Custom Integrated Circuits Conference, pp. 215-218, September 2009.
[24]  K. Shinkai and M. Hashimoto, ``A Gate Delay Model Focusing on Current Fluctuation Over Wide-Range of Process and Environmental Variability,'' In Proc. International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pp. 79-84, February 2009.
[25]  H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction,'' In Proc. Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 266-271, January 2009.
[26]  T. Enami, M. Hashimoto, and T. Sato, ``Decoupling Capacitance Allocation for Timing with Statistical Noise Model and Timing Analysis,'' In Proc. IEEE/ACM International Conference on Computer-Aided Design, pp. 420-425, November 2008.
[27]  H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``Vth Variation Modeling and Its Validation with Ring Oscillation Frequencies for Body-Biased Circuits and Subthreshold Circuits,'' In ICCAD Colocated Workshop on Test Structure Design for Variability Characterization, November 2008.
[28]  H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``Correlation Verification between Transistor Variability Model with Body Biasing and Ring Oscillation Frequency in 90nm Subthreshold Circuits,'' In Proc. IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), pp. 3-8, August 2008.
[29]  K. Hamamoto, H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``Experimental Study on Body-Biasing Layout Style - Negligible Area Overhead Enables Sufficient Speed Controllability -,'' In ACM Great Lakes Symposium on VLSI, pp. 387-390, May 2008.
[30]  T. Enami, S. Ninomiya, and M. Hashimoto, ``Statistical Timing Analysis Considering Spatially and Temporally Correlated Dynamic Power Supply Noise,'' In Proc. ACM International Symposium on Physical Design, pp. 160-167, April 2008.
[31]  S. Abe, M. Hashimoto, and T. Onoye, ``Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution,'' In Proc. International Symposium on Quality Electronic Design (ISQED), pp. 520-525, March 2008.
[32]  Y. Ogasahara, M. Hashimoto, and T. Onoye, ``Dynamic Supply Noise Measurement Circuit Composed of Standard Cells Suitable for In-Site Soc Power Integrity Verification,'' In Proc. IEEE/ACM Asia and South Pacific Design Automation Conference, pp. 107-108, January 2008.
[33]  K.Hamamoto, H.Fuketa, M.Hashimoto, Y.Mitsuyama, and T.Onoye, ``A Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability,'' In Proc. Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI 2007), pp. 233-237, October 2007.
[34]  Y. Ogasahara, M. Hashimoto, and T. Onoye, ``Dynamic Supply Noise Measurement with All Digital Gated Oscillator for Evaluating Decoupling Capacitance Effect,'' In Proc. IEEE Custom Integrated Circuits Conference, pp. 783-786, September 2007.
[35]  T. Kanamoto, Y. Ogasahara, K. Natsume, K. Yamaguchi, H. Amishiro, T. Watanabe, and M. Hashimoto, ``Impact of Well Edge Proximity Effect on Timing,'' In Proc. IEEE European Solid-State Device Research Conference, pp. 115-118, September 2007.
[36]  M. Hashimoto, J. Siriporn, A. Tsuchiya, H. Zhu, and C.-K. Cheng, ``Analytical Eye-Diagram Model for On-Chip Distortionless Transmission Lines and Its Application to Design Space Exploration,'' In Proc. IEEE Custom Integrated Circuits Conference, pp. 869-872, September 2007.
[37]  K. Shinkai, M. Hashimoto, and T. Onoye, ``Future Prediction of Self-Heating in Short Intra-Block Wires,'' In Proc. International Symposium on Quality Electronic Design (ISQED), pp. 660-665, March 2007.
[38]  K. Shinkai, M. Hashimoto, A. Kurokawa, and T. Onoye, ``A Gate Delay Model Focusing on Current Fluctuation Over Wide-Range of Process and Environmental Variability,'' In Proc. International Conference on Computer-Aided Design (ICCAD), pp. 47-53, November 2006.
[39]  Y. Ogasahara, M. Hashimoto, and T. Onoye, ``Quantitative Prediction of On-Chip Capacitive and Inductive Crosstalk Noise and Discussion on Wire Cross-Sectional Area Toward Inductive Crosstalk Free Interconnects,'' Proc. IEEE International Conference on Computer Design, pp. 70--75, October 2006.
[40]  Y. Ogasahara, M. Hashimoto, and T. Onoye, ``Measurement of Inductive Coupling Effect on Timing in 90nm Global Interconnects,'' In Proc. IEEE Custom Integrated Circuits Conference, pp. 721--724, September 2006.
[41]  Y. Ogasahara, T. Enami, M. Hashimoto, T. Sato, and T. Onoye, ``Measurement Results of Delay Degradation Due to Power Supply Noise Well Correlated with Full-Chip Simulation,'' In Proc.~IEEE Custom Integrated Circuits Conference, pp. 861--864, September 2006.
[42]  T. Ijichi, M. Hashimoto, S. Takahashi, S. Tsukiyama, and I. Shirakawa, ``Transistor Sizing of Lcd Driver Circuit for Technology Migration,'' In Proceedings of International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), vol. 1, p. I25--I28, July 2006.
[43]  T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, and M. Hashimoto, ``Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in Soc Design,'' In Proceedings of IEEE Wrokshop on Signal Propagation on Interconnects (SPI), pp. 227--230, May 2006.
[44]  K. Shinkai, M. Hashimoto, A. Kurokawa, and T. Onoye, ``A Gate Delay Model Focusing on Current Fluctuation Over Wide-Range of Process and Environmental Variability,'' In Proc. International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pp. 59-64, February 2006.
[45]  T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, and M. Hashimoto, ``Effective Si-Substrate Modeling for Frequency-Dependent Interconnect Resistance and Inductance Extraction,'' In The 3rd International Workshop on Compact Modeling, pp. 51--56, January 2006.
[46]  Y. Ogasahara, M. Hashimoto, and T. Onoye, ``Measurement and Analysis of Delay Variation Due to Inductive Coupling,'' In Proc. IEEE Custom Integrated Circuits Conference, pp. 305--308, September 2005.
[47]  Y. Uchida, S. Tani, M. Hashimoto, S. Tsukiyama, and I. Shirakawa, ``Interconnect Capacitance Extraction for System LCD Circuits,'' In in Proc. IEEE/ACM Great Lake Symposium on Very Large Scale Integrated circuits (GLSVLSI 2005), pp. 160--163, April 2005.
[48]  S. Takahashi, A. Taji, S. Tsukiyama, M. Hashimoto, and I. Shirakawa, ``A Sampling Switch Design for Liquid Crystal Displays,'' In Proceedings of IEEE International Region 10 Conference, 1C-03.3, 2005.
[49]  S. Takahashi, A. Taji, S. Tsukiyama, M. Hashimoto, and I. Shirakawa, ``A Design Scheme for Sampling Switch in Active Matrix LCD,'' In Proceedings of European Conference on Circuit Theory and Design, 3e-212, 2005.
研究会等発表論文
[1]  白井 僚,廣瀬 哲也,橋本 昌宜, ``超小型IoTノード向けアンテナ組み込み型OOKトランスミッタの実装と評価,'' 第45回アナログRF研究会, p. 2, March 2017.
[2]  郡浦 宏明, 今川 隆司, 密山 幸男, 橋本 昌宜, 尾上 孝雄, ``動作合成に対応した信頼性可変混合粒度再構成可能アーキテクチャの検討,'' 信学技報, RECONF2013-8, vol. 113, no. 52, pp. 41-46, May 2013.
[3]  天木 健彦, 橋本 昌宜, 密山 幸男, 尾上 孝雄, ``確率的動作モデルを用いたオシレータベース真性乱数生成回路のワーストケース設計手法,'' 信学技報, VLD2012-154, vol. 112, no. 451, pp. 099-104, March 2013.
[4]  郡浦 宏明, 今川 隆司, 密山 幸男, 橋本 昌宜, 尾上 孝雄, ``動的部分再構成による故障回避に関する一考察,'' 信学技報, RECONF2012-59 , vol. 112, no. 325, pp. 71-76, November 2012.
[5]  天木 健彦, 橋本 昌宜, 尾上 孝雄, ``ゆらぎ増幅回路を用いたオシレータベース物理乱数生成器,'' 信学技報, ICD2011-118, vol. 111, no. 352, pp. 087-092, December 2011.
[6]  郡浦 宏明, 密山 幸男, 橋本 昌宜, 尾上 孝雄, ``動的再構成可能アーキテクチャによる故障回避機構の定量的評価,'' 信学技報, RECONF2011-6, vol. 111, no. 31, pp. 31-36, May 2011.
[7]  天木 健彦, 橋本 昌宜, 密山 幸男, 尾上 孝雄, ``確率的動作モデルを用いたオシレータベース物理乱数生成器の設計手法,'' 情報処理学会研究報告, SLDM2010-147, vol. 2010-SLDM-147, no. 19, pp. 1-6, November 2010.
[8]  榎並 孝司, 木村 修太, 橋本 昌宜, 尾上 孝雄, ``自己性能補償に向けたカナリアFF挿入手法,'' 情報処理学会DAシンポジウム, pp. 227-232, September 2010.
[9]  高井 康充, 橋本 昌宜, 尾上 孝雄, ``電源ノイズに注目した電源遮断法の実機評価,'' , no. 信学技報 vol.110, No344, 電子情報通信学会(IEICE), 2010.
[10]  黒田 弾, 更田 裕司, 橋本 昌宜, 尾上 孝雄, ``低エネルギー動作に適した超低電圧プロセッサのアーキテクチャ評価,'' 情報処理学会第141回システムLSI設計技術研究会, pp107-112, October 2009.
[11]  新開 健一, 橋本 昌宜, ``広範囲な製造・環境ばらつきに対応したゲート遅延モデル,'' 情報処理学会DAシンポジウム, pp. 73-78, August 2009.
[12]  橋本 昌宜, 榎並 孝司, 新開 健一, 二宮 進有, 阿部 慎也, ``電源ノイズや製造ばらつきによるクロックジッタ・スキューを考慮した統計的タイミング解析,'' 情報処理学会DAシンポジウム, pp. 79-84, August 2009.
[13]  天木 健彦, 橋本 昌宜, 密山 幸男, 尾上 孝雄, ``マルコフモデルによるオシレータサンプリング方式真性乱数生成器の乱数品質解析,'' 第22回回路とシステム軽井沢ワークショップ, pp. 474-479, April 2009.
[14]  濱本 浩一, 橋本 昌宜, 密山 幸男, 尾上 孝雄, ``レイアウトを考慮した基板バイアスクラスタリング手法,'' 信学技報, VLD2008-159 , vol. 108, no. 478, pp. 195-200, March 2009.
[15]  榎並 孝司, 橋本 昌宜, 佐藤 高史, ``電源ノイズ考慮統計的タイミング解析を用いたデカップリング容量割当手法,'' 信学技報, VLD2008-161, vol. 108, no. 478, pp. 207-212, March 2009.
[16]  更田 裕司, 橋本 昌宜, 密山 幸男, 尾上 孝雄, ``サブスレッショルド回路における基板バイアスを考慮したトランジスタのばらつきモデリングとリングオシレータを用いた検証,'' 信学技報, VLD2008-159, vol. 108, no. 478, pp. 201-206, March 2009.
[17]  更田 裕司, 橋本 昌宜, 密山 幸男, 尾上 孝雄, ``タイミングエラー予告を用いた適応的速度制御におけるタイミングエラー頻度と消費電力のトレードオフ解析,'' 情報処理学会DAシンポジウム, pp. 217-222, August 2008.
[18]  濱本 浩一, 更田 裕司, 橋本 昌宜, 密山 幸男, 尾上 孝雄, ``基板バイアス印加レイアウト方式の面積効率と速度制御性の評価,'' 信学技報, CAS2008-14, VLD2008-27, SIP2008-48(2008-6), pp. 75-79, June 2008.
[19]  小笠原泰弘, 橋本昌宜, 尾上孝雄, ``バス配線による誘導性クロストークノイズによる遅延変動の実測とノイズ重ねあわせ効果の検証,'' , 信学技報, VLD2007-153, March 2008.
[20]  小笠原 泰弘, 橋本 昌宜, 尾上 孝雄, ``スタンダードセルで構成された電源ノイズ波形測定回路の提案,'' 信学技報, CPM2007-131, ICD2007-142, pp. 17-22, January 2008.
[21]  二宮 進有, 橋本 昌宜, ``SSTAにおける空間的相関を持つ製造ばらつきのグリッドベースモデル化法の検討,'' 信学技報, VLD2007-91, DC2007-46, vol. 107, no. 336, pp. 13-17, November 2007.
[22]  阿部 慎也, 橋本 昌宜, 尾上 孝雄, ``製造ばらつきを考慮したメッシュ型クロック分配網のスキュー評価,'' 情報処理学会DAシンポジウム, pp. 133-138, August 2007.
[23]  新開 健一, 橋本 昌宜, 尾上 孝雄, ``短距離ブロック内配線の自己発熱,'' 第 20 回 回路とシステム軽井沢ワークショップ, pp. 7-12, April 2007.
[24]  榎並 孝司, 二宮 進有, 橋本 昌宜, ``電源ノイズの空間的相関を考慮した統計的タイミング解析,'' 第20回 回路とシステム軽井沢ワークショップ, pp. 667-672, April 2007.
[25]  小笠原 泰弘, 橋本 昌宜, 尾上 孝雄, ``90nm グローバル配線における誘導性クロストークノイズによる遅延変動の実測,'' 信学技報, CPM2006-131, ICD2006-173, pp. 13--18, January 2007.
[26]  小笠原 泰弘, 榎並 孝司, 橋本 昌宜, 佐藤 高史, 尾上 孝雄, ``電源ノイズによる遅延変動の測定と電源ノイズを再現するフルチップシミュレーション手法,'' 信学技報, CPM2006-132, ICD2006-174, pp. 19--23, January 2007.
[27]  Jangsombatsiri Siriporn, 橋本 昌宜, 尾上 孝雄, ``シャントコンダクタンスを挿入したオンチップ伝送線路特性評価,'' 第十回シリコンアナログRF研究会, November 2006.
[28]  榎並 孝司, 橋本 昌宜, 尾上 孝雄, ``主成分分析による電源電圧変動の統計的モデル化手法,'' 情報処理学会DAシンポジウム, pp. 205--210, July 2006.
[29]  新開 健一, 橋本 昌宜, 黒川 敦, 尾上孝雄, ``電流変動に着目した広範囲な製造・環境ばらつき対応ゲート遅延モデル,'' 第19回 回路とシステム軽井沢ワークショップ, pp. 559-564, April 2006.
[30]  小笠原泰弘, 橋本昌宜, 尾上孝雄, ``LSI配線における容量性, 誘導性クロストークノイズの定量的将来予測,'' 第19回回路とシステム軽井沢ワークショップ, pp. 5--10, April 2006.
[31]  伊地知孝仁, 橋本昌宜, 高橋真吾, 築山修治, 白川功, ``画素充電率制約を満足する液晶ドライバ回路のトランジスタサイズ決定技術,'' 信学技報, VLD2005-131, pp. 55--60, March 2006.
[32]  小笠原泰弘, 橋本昌宜, 尾上孝雄, ``誘導性・容量性クロストークノイズによる遅延変動の測定と評価,'' 信学技報, SDM2005-135, ICD2005-74, pp. 43--48, August 2005.
[33]  内田 好弘, 谷 貞宏, 橋本 昌宜, 築山 修治, 白川 功, ``システム液晶のための配線間容量抽出手法,'' 信学技報, VLD2004-64, pp. 19--24, December 2004.
大会等発表論文
[1]  榎並 孝司, 橋本 昌宜, ``統計的電源ノイズモデル化に適した適応的領域分割法,'' 電子情報通信学会ソサイエティ大会, pp. A-3-10, September 2007.
[2]  二宮 進有, 橋本 昌宜, ``空間的相関を考慮したSSTAにおける領域の分割数と精度,'' 電子情報通信学会総合大会, A-3-1 , March 2007.
[3]  濱本 浩一, 橋本 昌宜, 密山 幸男, 尾上 孝雄, ``低電圧回路向け基板電位制御レイアウト方式の面積効率評価,'' 電子情報通信学会総合大会, A-3-6, March 2007.
[4]  阿部 慎也, 橋本 昌宜, 尾上 孝雄, ``メッシュ型クロック分配網のスキュー評価,'' 電子情報通信学会総合大会, A-3-5, March 2007.
[5]  更田 裕司, 橋本 昌宜, 密山 幸男, 尾上 孝雄, ``加算器を用いたsubthreshold 回路の設計指針の検討,'' 電子情報通信学会総合大会, A-3-17, March 2007.
[6]  Siriporn Jangsombatsiri, 橋本昌宜, 土谷亮, Haikun Zhu, Chung-Kuan Cheng, ``シャントコンダクタンスを挿入したオンチップ伝送線路のアイパターン評価,'' 電子情報通信学会総合大会, A-3-9, March 2007.
[7]  新開 健一, 橋本 昌宜, 尾上 孝雄, ``短距離ブロック内配線の自己発熱問題の将来予測,'' 電子情報通信学会ソサイエティ大会, pp. A-3-14, September 2006.
[8]  榎並 孝司, 橋本 昌宜, 尾上 孝雄, ``電源ノイズ解析のための回路動作部表現法の評価,'' 電子情報通信学会総合大会, A-3-16, March 2006.
[9]  高橋 真吾, 築山 修治, 橋本 昌宜, 白川 功, ``液晶ディスプレイ用サンプリング回路の設計手法について,'' 2005 年電子情報通信学会ソサイエティ大会講演論文集, A-3-4, 2005.
[10]  内田 好弘, 谷 貞宏, 橋本 昌宜, 築山 修治, 白川 功, ``システム液晶に適した配線間容量抽出の検討,'' 電子情報通信学会ソサイエティ大会, A-1-16, September 2004.

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