論文誌
[1]  S. Tani, Y. Uchida, M. Furuie, S. Tsukiyama, B. Lee, S. Nishi, Y. Kubota, I. Shirakawa, and S. Imai, ``Parasitic Capacitance Modeling for Non-Planar Interconnects in Liquid Crystal Displays,'' IEICE Trans. on Fundamentals, vol. E86-A, no. 12, pp. 2923--2932, December 2003.
[2]  B.Y. Song, M. Furuie, Y. Yoshida, T. Onoye, and I. Shirakawa, ``Low-Power VLSI Implementation by NMOS 4-Phase Dynamic Logic,'' Trans. of IPSJ, vol. 41, no. 4, pp. 899--907, April 2000.
[3]  松村 謙次, 古家 眞, 藤田 玄, 正城 敏博, 白川 功, 稲田 紘, ``医療用監視システムとその通信制御用 LSI の設計,'' 情報処理学会論文誌, vol. 41, no. 4, pp. 962--969, April 2000.
[4]  B.Y. Song, M. Furuie, Y. Yoshida, T. Onoye, and I. Shirakawa, ``Low-Power Scheme of NMOS 4-Phase Dynamic Logic,'' IEICE Trans. Electron., vol. E82--C, no. 9, pp. 1772--1776, September 1999.
国際会議
[1]  S. Tani, Y. Uchida, M. Furuie, S. Tsukiyama, B. Lee, S. Nishi, Y. Kubota, I. Shirakawa, and S. Imai, ``A Parasitic Capacitance Modeling Method for Non-Planar Interconnects,'' In in Proc. the Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI 2003), pp. 294--299, April 2003.
[2]  S. Tani, Y. Uchida, M. Furuie, S. Tsukiyama, B. Lee, S. Nishi, Y. Kubota, I. Shirakawa, and S. Imai, ``Parasitic Capacitance Modeling for Multilevel Interconnects,'' In in Proc. IEEE Proceedings of Asia-Pacific Conference on Circuits and Systems 2002, vol. 1, pp. 59--64, December 2002.
[3]  M. Furuie, T. Onoye, S. Tsukiyama, and I. Shirakawa, ``Two-Dimensional Array Layout for NMOS 4-Phase Dynamic Logic,'' In in Proc. The 8th IEEE International Conference on Electronics, Circuits and Systems(ICECS 2001), Malta, pp. 589--592, September 2001.
[4]  R. Y. Omaki, Y. Dong, M. H. Miki, M. Furuie, D. Taki, M. Tarui, G. Fujita, T. Onoye, and I. Shirakawa, ``Realtime Wavelet Video Coder Based on Reduced Memory Accessing,'' In in Proc.~Asia and South Pacific Design Automation Conference (ASP-DAC 2001), Yokohama, Japan, pp. 15--16, January 2001.
[5]  R. Y. Omaki, Y. Dong, M. H. Miki, M. Furuie, S. Yamada, D. Taki, M. Tarui, G. Fujita, T. Onoye, and I. Shirakawa, ``VLSI Implementation of a Realtime Wavelet Video Coder,'' In in Proc. Custom Integrated Circuits Conference (CICC 2000), Florida, USA, pp. 543--546, May 2000.
[6]  M. Furuie, B. Y. Song, Y. Yoshida, T. Onoye, and I. Shirakawa, ``Layout Generation of Array Cell for NMOS 4-Phase Dynamil Logic,'' In in Proc. ASP-DAC2000, pp. 529--532, January 2000.
[7]  M. Furuie, B. Y. Song, Y. Yoshida, T. Onoye, and I. Shirakawa, ``Layout Generation for Low-Power NMOS 4-Phase Dynamic Logic Array,'' In in Proc. IEEE Region 10 Conference (TENCON '99), pp. 872--875, September 1999.
[8]  B. Y. Song, M. Furuie, Y. Yoshida, T. Onoye, and I. Shirakawa, ``Array Macro Cell Architecture for Low-Power NMOS 4-Phase Dynamic Logic,'' In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC '99), Sado, Japan, pp. 561--564, July 1999.
[9]  J. Fan, G. Fujita, M. Furuie, T. Onoye, and I. Shirakawa, ``Structual Objeco-Oriented Video Segmentation and Representation Algorithm,'' In in Proc. IEEE International Workshop on Intelligent Signal Processing and Communication Systems, pp. 78--82, November 1998.
[10]  M. Furuie, T. Onoye, S. Tsukiyama, and Isao Shirakawa, ``Two-Dimensional Array Layout for Low Power NMOS 4-Phase Dynamic Logic,'' In in Proc. International Conference on Electronics Packaging(2001 ICEP), Tokyo, April, 2001., pp. 417--421, .
研究会等発表論文
[1]  古家 眞, 宋 宝玉, 吉田 幸弘, 尾上 孝雄, 白川 功, ``4相NMOSダイナミックロジック用アレイセル,'' 信学技報, CAS99-62, pp. 1--6, September 1999.
[2]  古家 眞, 松村 謙次, 藤田 玄, 正城 敏博, 白川 功, 稲田 紘, ``医療用監視システムのための通信制御用LSI,'' 信学技報, CAS99, pp. 15--19, June 1999.

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