論文誌
[1]  K. Miyanohana, G. Fujita, K. Yanagida, T. Onoye, and I. Shirakawa, ``Single Chip Implementation of Encoder-Decoder for Low Bit Rate Visural Communication,'' J. Circuits, Systems, and Computers, vol. 7, no. 5, pp. 441-457, May 1997.
国際会議
[1]  J. Fan, G. Fujita, J. Yu, K. Miyanohana, T. Onoye, N. Ishiura, L. Wu, and I. Shirakawa, ``Hierarchical Object-Oriented Image and Video Segmentation Algorithm Based on 2D Entropic Thresholding,'' In in Proc. Electronic Imaging and Multimedia Systems II, SPIE, pp. 141--151, September 1998.
[2]  K. Miyanohana, G. Fujita, K. Yanagida, T. Onoye, and I. Shirakawa, ``VLSI Implementation of Single Chip Encoder/Decoder for Low Bitrate Visual Communication,'' In in Proc. IEEE Custom Integrated Circuits Conference, pp. 229-232, May 1997.
[3]  K. Miyanohana, G. Fujita, T. Onoye, and I. Shirakawa, ``VLSI Implementation of Edge Detector and Vector Quantizer for Very Low Bitrate Video Encoding,'' In in Proc. IEEE Asia Pacific Conference on Circuits and Systems (APCCAS '96), pp. 480-483, November 1996.
[4]  K. Miyanohana, G. Fujita, T. Onoye, and I. Shirakawa, ``Implementation of Very Low Bitrate Video Encoder Core,'' In in Proc. 2nd International Conference on ASIC, pp. 131-134, October 1996.
[5]  K. Miyanohana, G. Fujita, T. Onoye, and I. Shirakawa, ``VLSI Architecture for Very Low Bitrate Video Encoder Core,'' In in Proc. Int'l Technical Conference on Circuits/Systems, Computers and Communications, pp. 294-297, July 1996.
研究会等発表論文
[1]  宮野鼻晃士, 藤田玄, 柳田和弘, 尾上孝雄, 白川 功, ``携帯環境向き低ビットレート動画像通信システムのVLSI 化設計,'' 電子情報通信学会技術研究報告, DSP97-107, vol. 97, no. 315, pp. 17-24, October 1997.
[2]  宮野鼻晃士, 藤田玄, 尾上孝雄, 白川功, ``低ビットレート画像符号化アルゴリズムとその VLSI 化設計,'' 電子情報通信学会技術研究報告, DSP96-89, vol. 96, no. 301, pp. 33-38, October 1996.
大会等発表論文
[1]  宮野鼻晃士, 柳田和弘, 尾上孝雄, 白川功, ``低ビットレート動画像通信システムのVLSI化設計,'' SCI第41回システム制御情報学会研究発表講演会, pp. 247-248, May 1997.

This site is maintained by Onoye Lab.

PMAN 2.5.5 - Paper MANagement system / (C) 2002-2008, Osamu Mizuno / All rights reserved.