論文誌
[1]  T. Uemura, T. Kato, R. Tanabe, H. Iwata, J. Ariyoshi, H. Matsuyama, and M. Hashimoto, ``Exploring Well-Configurations for Minimizing Single Event Latchup,'' IEEE Transactions on Nuclear Science, vol. 61, no. 6, pp. 3282--3289, December 2014.
[2]  T. Uemura, T. Kato, H. Matsuyama, and M. Hashimoto, ``Mitigating Multi-Bit-Upset with Well-Slits in 28 Nm Multi-Bit-Latch,'' IEEE Transactions on Nuclear Science, vol. 60, no. 6, pp. 4362--4367, December 2013.
[3]  T. Uemura, T. Kato, H. Matsuyama, and M. Hashimoto, ``Soft-Error in Sram at Ultra-Low Voltage and Impact of Secondary Proton in Terrestrial Environment,'' IEEE Transactions on Nuclear Science, vol. 60, no. 6, pp. 4232--4237, December 2013.
国際会議
[1]  T. Uemura, T. Kato, S. Okano, H. Matsuyama, and M. Hashimoto, ``Impact of Package on Neutron Induced Single Event Upset in 20 Nm Sram,'' Proceedings of International Symposium on Reliability Physics (IRPS), April 2015.
[2]  T. Uemura, S. Okano, T. Kato, H. Matsuyama, and M. Hashimoto, ``Soft Error Immune Latch Design for 20 Nm Bulk Cmos,'' Proceedings of International Reliability Physics Symposium (IRPS), April 2015.
[3]  T. Uemura, T. Kato, R. Tanabe, H. Iwata, J. Ariyoshi, H. Matsuyama, and M. Hashimoto, ``Optimizing Well-Configuration for Minimizing Single Event Latchup,'' IEEE Nuclear and Space Radiation Effects Conference (NSREC), July 2014.
[4]  T. Uemura, T. Kato, R. Tanabe, H. Iwata, H. Matsuyama, M. Hashimoto, K. Takahisa, M. Fukuda, and K. Hatanaka, ``Preventing Single Event Latchup with Deep P-Well on P-Substrate,'' Proceedings of International Reliability Physics Symposium (IRPS), June 2014.
[5]  T. Uemura, T. Kato, H. Matsuyama, and M. Hashimoto, ``Scaling Trend of Sram and Ff of Soft-Error Rate and Their Contribution to Processor Reliability on Bulk Cmos Technology,'' IEEE Nuclear and Space Radiation Effects Conference (NSREC), July 2013.
[6]  T. Uemura, T. Kato, H. Matsuyama, and M. Hashimoto, ``Soft-Error in Sram at Ultra Low Voltage and Impact of Secondary Proton in Terrestrial Environment,'' IEEE Nuclear and Space Radiation Effects Conference (NSREC), July 2013.
[7]  T. Uemura, T. Kato, H. Matsuyama, and M. Hashimoto, ``Mitigating Multi-Cell-Upset with Well-Slits in 28nm Multi-Bit-Latch,'' IEEE Nuclear and Space Radiation Effects Conference (NSREC), July 2013.
[8]  R. Hashimoto, K. Kato, G. Fujta, and T. Onoye, ``VLSI Architecture of H.264 RDO-Based Block Size Decision for 1080 HD,'' In Proc. PCS, November 2007.
[9]  R. Hashimoto, K. Kato, G. Fujta, and T. Onoye, ``VLSI Architecture of H.264 Block Size Decision Based on Rate-Distortion Optimization,'' In Proc. ISPACS, pp. 618--621, December 2006.
研究会等発表論文
[1]  加藤裕視, 山田晃久, 尾上孝雄, ``フレームメモリの削減を目的とした画像圧縮手法,'' 電子情報通信学会 CAS信学技報, vol. 107, no. 476, pp. 31-36, January 2008.
[2]  橋本亮司, 加藤公也, 才辻誠, 田中照人, 上津寛和, 藤田玄, 尾上孝雄, ``1080HD向けマルチシンボルH.264エントロピー復号器,'' 第21回ディジタル信号処理シンポジウム, November 2007.
[3]  加藤 公也, 橋本 亮司, 藤田 玄, 尾上 孝雄, ``H.264 High ProfileにおけるマルチシンボルCABAC復号器のアーキテクチャ検討,'' 信学技報, SIP2007-121, ICD2007-110, IE2007-80, pp. 65-70, October 2007.
大会等発表論文
[1]  橋本 亮司, 加藤 公也, 藤田 玄, 尾上 孝雄, ``H.264 CABAC復号器の高速化に関する一検討,'' 電子情報通信学会2008ソサイエティ大会,A-20-9, September 2008.
[2]  加藤 公也, 橋本 亮司, 藤田 玄, 尾上 孝雄, ``時間的・空間的隣接ヘッダ情報に基づくH.264イントラ予測モード判定手法,'' 電子情報通信学会ソサイエティ大会, September 2006.

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