論文誌
[1]  S. Yano, K. Akagi, H. Inohara, and N. Ishiura, ``Application of Full Scan Design to Embedded Memory Arrays,'' in Proc. IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, vol. E80-A, no. 3, March 1997.
研究会等発表論文
[1]  S. Yano, K. Akagi, and N. Ishiura, ``A New Scan Path Approach to Memory Array Testing,'' In 電子情報通信学会第9回回路とシステム軽 井沢ワークショップ, pp. 55-60, April 1996.

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