論文誌
[1]  H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction,'' IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, vol. E92-A, no. 12, pp. 3094-3102, December 2009.
[2]  Hiroki Sugano, Takahiko Masuzaki, Hiroshi Tsutsui, Takao Onoye, Hiroyuki Ochi, and Yukihiro Nakamura, ``Efficient Memory Organization Framework for Jpeg2000 Entropy Codec,'' IEICE Trans. Fundamentals, vol. E92-A, no. 8, pp. 1970-1977, August 2009.
[3]  増崎 隆彦, 筒井 弘, 尾上 孝雄, 水野 雄介, 佐々木 元, 中村 行宏, ``シングルタイル JPEG2000 コーデックのシステム構成,'' 画像電子学会誌, vol. 38, no. 3, pp. 296-304, May 2009.
[4]  K. Hamamoto, H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``An Experimental Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability,'' IEICE Trans. on Electronics, vol. E92-C, no. 2, pp. 281-285, February 2009.
[5]  Takahiko Masuzaki, Hiroshi Tsutsui, Quang Minh Vu, Takao Onoye, and Yukihiro Nakamura, ``JPEG2000 High-Speed SNR Progressive Decoding Scheme,'' International Journal of Computer Science and Network Security, vol. 9, no. 1, pp. 62-68, January 2009.
[6]  H. Tsutsui, T. Masuzaki, Y. Hayashi, Y. Taki, T. Izumi, T. Onoye, and Y. Nakamura, ``Design Framework for JPEG2000 System Architecture,'' In Journal of Intelligent Automation and Soft Computing, vol. 13, no. 3, pp. 331--343, March 2006.
[7]  H. Mizuno, H. Kobayashi, T. Onoye, and I. Shirakawa, ``Performance Estimation at Architecture Level for Embedded Systems,'' IEEE Transaction on Fundamentals of Electronics, Communications and Computer Sciences, vol. E85-A, no. 12, pp. 2636--2644, December 2002.
[8]  Hiroshi Tsutsui, Akihiko Tomita, Shigenori Sugimoto, Kazuhisa Sakai, Tomonori Izumi, Takao Onoye, and Yukihiro Nakamura, ``Lut-Array-Based Pld and Synthesis Approach Based on Sum of Generalized Complex Terms Expression,'' IEICE Trans. Fundamentals, vol. E84-A, no. 11, pp. 2681-2689, November 2001.
[9]  清水則一, 小山修治, 小野浩, 宮下耕一, 近藤仁志, 水田義明, ``GPS変位モニタリングシステムの連続観測における安定性の検証と計測結果 の処理方法の提案,'' 資源と素材, vol. 113, no. 7, pp. 549-554, July 1997.
国際会議
[1]  Tatsuo Maeno, Hiroshi Tsutsui, and Takao Onoye, ``Hardware Implementation of Real-Time Motion Adaptive Deinterlacing Based on Inpainting,'' In International Conference on Embedded Systems and Intelligent Technology, February 2011.
[2]  Hideyuki Nakamura, Hiroshi Tsutsui, and Takao Onoye, ``Motion-Compensated Frame Interpolation Using Feature Tracking and Motion Segmentation,'' In International Workshop on Smart Info-Media Systems in Asia, September 2010.
[3]  H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``Adaptive Performance Control with Embedded Timing Error Predictive Sensors for Subthreshold Circuits,'' In Proc. Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 361-362, January 2010.
[4]  H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``Adaptive Performance Compensation with In-Situ Timing Error Prediction for Subthreshold Circuits,'' In Proc. IEEE Custom Integrated Circuits Conference, pp. 215-218, September 2009.
[5]  H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction,'' In Proc. Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 266-271, January 2009.
[6]  H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``Vth Variation Modeling and Its Validation with Ring Oscillation Frequencies for Body-Biased Circuits and Subthreshold Circuits,'' In ICCAD Colocated Workshop on Test Structure Design for Variability Characterization, November 2008.
[7]  H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``Correlation Verification between Transistor Variability Model with Body Biasing and Ring Oscillation Frequency in 90nm Subthreshold Circuits,'' In Proc. IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), pp. 3-8, August 2008.
[8]  K. Hamamoto, H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, ``Experimental Study on Body-Biasing Layout Style - Negligible Area Overhead Enables Sufficient Speed Controllability -,'' In ACM Great Lakes Symposium on VLSI, pp. 387-390, May 2008.
[9]  K.Hamamoto, H.Fuketa, M.Hashimoto, Y.Mitsuyama, and T.Onoye, ``A Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability,'' In Proc. Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI 2007), pp. 233-237, October 2007.
[10]  J. Ashida, R. Miyamoto, H. Tsutsui, T. Onoye, and Y. Nakamura, ``Probabilistic Pedestrian Tracking Based on a Skeleton Model,'' In Proc. International Conference on Image Processing, pp. 2825--2828, October 2006.
[11]  F. Hyuga, T. Masuzaki, H. Tsutsui, T. Onoye, and Y. Nakamura, ``A JPEG Coding Scheme for High Fidelity Images by Halftoning Less Signification Extra Bits,'' In Proc. International Technical Conference on Circuits/Systems, Computers and Communication, vol. , pp. 97--100, July 2006.
[12]  H. Sugano, H. Tsutsui, T. Masuzaki, T. Onoye, H. Ochi, and Y. Nakamura, ``Efficient Memory Architecture for JPEG2000 Entropy Codec,'' In Proc. International Symposium on Circuits and Systems, pp. 2881--2884, May 2006.
[13]  R. Miyamoto, H. Sugita, Y. Hayashi, H. Tsutsui, T. Masuzaki, T. Onoye, and Y. Nakamura, ``High Quality Motion JPEG2000 Coding Scheme Based on the Human Visual System,'' In Proc. IEEE Int’l Symp. Circuits and Systems, pp. 2096--2099, May 2005.
[14]  R. Miyamoto, Y. Hayashi, H. Tsutsui, T. Masuzaki, T. Onoye, and Y. Nakamura, ``Video Quality Enhancement for Motion JPEG2000 Encoding Based on the Human Visual System,'' In Proc. IEEE Asia Pacific Conference on Circuits and Systems, pp. 1161--1164, December 2004.
[15]  H. Tsutsui, T. Masuzaki, Y. Hayashi, Y. Taki, T. Izumi, T. Onoye, and Y. Nakamura, ``Scalable Design Framework for JPEG2000 System Architecture,'' In Proc. Asia-Pacific Computer Systems Architecture Conference, pp. 6--11, September 2004.
[16]  J. Ashida, R. Miyamoto, H. Tsutsui, T. Onoye, and Y. Nakamura, ``A Scalable Approach for Estimation of Focus of Expansion,'' In Proc. IASTED International Conference on Visualization, Imaging, and Image Processing, pp. 6--11, September 2004.
[17]  T. Onoye, H. Tsutsui, G. Fujita, Y. Nakamura, and I. Shirakawa, ``Embedded System Implementation of Scalable and Object-Based Video Coding,'' In in Proc. of World Automation Congress (WAC) , International Forum on Multimedia and Image Processing (IFMIP), IFMIP076, June 2004.
[18]  H. Sugita, Q.-M. Vu, T. Masuzaki, H. Tsutsui, T. Izumi, T. Onoye, and Y. Nakamura, ``JPEG2000 High-Speed Progressive Decoding Scheme,'' In Proc. IEEE International Symposium on Circuits and Systems, pp. 873--876, May 2004.
[19]  Y. Hayashi, H. Tsutsui, T. Masuzaki, T. Izumi, T. Onoye, and Y. Nakamura, ``Design Framework for JPEG2000 Encoding System Architecture,'' In Proc. International Symposium on Circuits and Systems, pp. 740--743, May 2003.
[20]  Y. Hayashi, H. Tsutsui, T. Masuzaki, T. Izumi, T. Onoye, and Y. Nakamura, ``Scalable Design Framework for JPEG2000 Encoder Architecture,'' In Proc. Workshop on Synthesis and System Integration of Mixed Information Technologies, pp. 372--376, April 2003.
[21]  H. Mizuno, H. Kobayashi, T. Onoye, and I. Shirakawa, ``Power Estimation at Architecture Level for Embedded Systems,'' In ibid, vol. II, pp. 476--479, May 2002.
[22]  H. Mizuno, H. Kobayashi, T. Onoye, and I. Shirakawa, ``An Architecture Level Power Estimation Method for Embedded Systems,'' In in Proc. Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI 2001), Nara, Japan, pp. 78--85, October 2001.
[23]  N. Shimizu, Y. Mizuta, H. Kondo, and H. Ono, ``A New GPS Real-Time Monitoring System for Deformation Measurements and Its Application,'' In in Proc. 8th FIG Int. Symp. Deformation Measurements, Hong Kong, S1.5, pp. 47-54, June 1996.
研究会等発表論文
[1]  黒田 弾, 更田 裕司, 橋本 昌宜, 尾上 孝雄, ``低エネルギー動作に適した超低電圧プロセッサのアーキテクチャ評価,'' 情報処理学会第141回システムLSI設計技術研究会, pp107-112, October 2009.
[2]  更田 裕司, 橋本 昌宜, 密山 幸男, 尾上 孝雄, ``サブスレッショルド回路における基板バイアスを考慮したトランジスタのばらつきモデリングとリングオシレータを用いた検証,'' 信学技報, VLD2008-159, vol. 108, no. 478, pp. 201-206, March 2009.
[3]  橋本亮司, 筒井 弘, 尾上孝雄, 猪飼知宏, ``DCT領域 Distributed Video Coding における尤度推定手法,'' 信学技報, IE2008-209, vol. 108, no. 425, pp. 31-36, February 2009.
[4]  更田 裕司, 橋本 昌宜, 密山 幸男, 尾上 孝雄, ``タイミングエラー予告を用いた適応的速度制御におけるタイミングエラー頻度と消費電力のトレードオフ解析,'' 情報処理学会DAシンポジウム, pp. 217-222, August 2008.
[5]  濱本 浩一, 更田 裕司, 橋本 昌宜, 密山 幸男, 尾上 孝雄, ``基板バイアス印加レイアウト方式の面積効率と速度制御性の評価,'' 信学技報, CAS2008-14, VLD2008-27, SIP2008-48(2008-6), pp. 75-79, June 2008.
[6]  加藤裕視, 山田晃久, 尾上孝雄, ``フレームメモリの削減を目的とした画像圧縮手法,'' 電子情報通信学会 CAS信学技報, vol. 107, no. 476, pp. 31-36, January 2008.
[7]  筒井 弘, 藤田 憲正, 尾上 孝雄, 中村 行宏, ``JPEG2000 マルチシンボル算術復号器,'' 信学技報, SIS2007-3, vol. 107, no. 93, pp. 13--18, June 2007.
[8]  水野 洋, 小林 弘幸, 尾上 孝雄, 白川 功, ``組込みシステムアーキテクチャレベルにおける消費電力見積り手法,'' 電子情報通信学会 第15回 回路とシステム(軽井沢)ワークショップ, pp. 435--440, April 2002.
[9]  清水則一, 近藤仁志, 宮下耕一, 小野浩, ``GPS地盤変位モニタリングシステムによる残壁の長期観測実験,'' 第28回岩盤力学に関するシンポジウム講演論文集, pp. 388-392, January 1997.
[10]  佐藤洋, 森本康夫, 正城敏博, 尾上孝雄, 白川功, ``1チップ MPEG2 デコーダの設計と動き補償器の VLSI 実装,'' 情報処理学会DAシンポジウム'96, pp. 47-52, August 1996.
[11]  清水則一, 小野浩, 近藤仁志, 水田義明, ``長大残壁の安全監視へのGPS変位計測システムの応用に関する現場実験,'' 資源と素材, vol. 112, pp. 283-288, May 1996.
大会等発表論文
[1]  中村 秀幸, 筒井 弘, 橋本 亮司, 尾上 孝雄, ``特徴点追跡を用いた動き補償フレーム補間手法,'' 電子情報通信学会2009ソサイエティ大会, A-20-14, p. 204, September 2009.
[2]  更田 裕司, 橋本 昌宜, 密山 幸男, 尾上 孝雄, ``加算器を用いたsubthreshold 回路の設計指針の検討,'' 電子情報通信学会総合大会, A-3-17, March 2007.
[3]  小林 弘幸, 水野 洋, 尾上 孝雄, 白川 功, ``組込みシステムにおける消費電力見積りの一手法,'' 信学会 ソサイエティ大会, SA-1-1, September 2001.

This site is maintained by Onoye Lab.

PMAN 2.5.5 - Paper MANagement system / (C) 2002-2008, Osamu Mizuno / All rights reserved.