論文誌
[1]  D. Fukuda, K. Watanabe, Y. Kanazawa, and M. Hashimoto, ``Modeling the Effect of Global Layout Pattern on Wire Width Variation for On-The-Fly Etching Process Modification,'' IEICE Trans. Fundamentals of Electronics Communications and Computer Sciences, vol. E98-A, no. 7, pp. 1467--1474, July 2015.
[2]  D. Fukuda, K. Watanabe, N. Idani, Y. Kanazawa, and M. Hashimoto, ``Edge-Over-Erosion Error Prediction Method Based on Multi-Level Machine Learning Algorithm,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E97-A, no. 12, pp. 2373--2382, December 2014.
[3]  T. Uemura, T. Kato, R. Tanabe, H. Iwata, J. Ariyoshi, H. Matsuyama, and M. Hashimoto, ``Exploring Well-Configurations for Minimizing Single Event Latchup,'' IEEE Transactions on Nuclear Science, vol. 61, no. 6, pp. 3282--3289, December 2014.
[4]  R. Harada, S. Abe, H. Fuketa, T. Uemura, M. Hashimoto, and Y. Watanabe, ``Angular Dependency of Neutron Induced Multiple Cell Upsets in 65-Nm 10t Subthreshold Sram,'' IEEE Transactions on Nuclear Science, vol. 59, no. 6, pp. 2791--2795, December 2012.
[5]  T. Enami, S. Ninomiya, K. Shinkai, S. Abe, and M. Hashimoto, ``Statistical Timing Analysis Considering Clock Jitter and Skew Due to Power Supply Noise and Process Variation,'' IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, vol. 93-A, no. 12, pp. 2399-2408, December 2010.
[6]  渡邊 賢治, 達可 敏充, 畠中 理英, 尾上 孝雄, ``屋内位置推定システムのための間取り推定手法,'' Journal of Signal Processing, vol. 14, no. 3, pp. 231-242, May 2010.
[7]  畠中 理英, 達可 敏充, 渡邊 賢治, 尾上 孝雄, ``透過減衰を考慮した無線ホームネットワーク向け位置推定,'' 情報処理学会論文誌, vol. 50, no. 8, p. 1835–1844, August 2009.
[8]  T. Kanamoto, Y. Ogasahara, K. Natsume, K. Yamaguchi, H. Amishiro, T. Watanabe, and M. Hashimoto, ``Impact of Well Edge Proximity Effect on Timing,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E91-A, no. 12, pp. 3461-3464, December 2008.
[9]  S. Abe, M. Hashimoto, and T. Onoye, ``Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E91-A, no. 12, pp. 3481-3487, December 2008.
[10]  R. Hashimoto, T. Matsumura, Y. Nozato, K. Watanabe, and T. Onoye, ``Implementation of Multi-Agent Object Attention System Based on Biologically Inspired Attractor Selection,'' IEICE Trans. Fundamentals, vol. E91-A, no. 10, October 2008.
[11]  M. Ise, Y. Ogasahara, K. Watanabe, M. Hatanaka, T. Onoye, H. Niwamoto, I. Keshi, and I. Shirakawa, ``Design and Implementation of Home Network Protocol for Appliance Control Based on IEEE 802.15.4,'' International Journal of Computer Science and Network Security, vol. 7, no. 7, pp. 20-30, July 2007.
[12]  K. Watanabe, M. Ise, T. Onoye, H. Niwamoto, and I. Keshi, ``An Energy-Efficient Architecture of Wireless Home Network Based on Mac Broadcast and Transmission Power Control,'' In IEEE Trans. Consumer Electronics, vol. 53, no. 1, pp. 124--130, February 2007.
[13]  T. Watanabe and N. Ishiura, ``Resister Constraint Analysis to Minimize Spill Code for Application Specific DSPs,'' IEICE Trans. Fundamentals of Electronics Communications and Computer Sciences, vol. E84-A, no. 6, pp. 1541--1544, June 2001.
[14]  K. Kawamoto, S. Mizuno, H. Abe, Y. Higuchi, H. Ishihara, H. Fukumoto, T. Watanabe, S. Fujino, and I. Shirakawa, ``A Single Chip Automotive Control LSI Using SOI Bipolar Complimentary MOS Double-Diffused MOS,'' The Japan Society of Applied Physics, vol. 40, no. 4B, pp. 2891--2896, April 2001.
国際会議
[1]  S. Hirokawa, R. Harada, M. Hashimoto, K. Sakuta, and Y. Watanabe, ``Neutron-Induced Seu and Mcu Rate Characterization and Analysis of Sotb and Bulk Srams at 0.3v Operation,'' IEEE Nuclear and Space Radiation Effects Conference (NSREC), July 2015.
[2]  T. Uemura, T. Kato, R. Tanabe, H. Iwata, J. Ariyoshi, H. Matsuyama, and M. Hashimoto, ``Optimizing Well-Configuration for Minimizing Single Event Latchup,'' IEEE Nuclear and Space Radiation Effects Conference (NSREC), July 2014.
[3]  T. Uemura, T. Kato, R. Tanabe, H. Iwata, H. Matsuyama, M. Hashimoto, K. Takahisa, M. Fukuda, and K. Hatanaka, ``Preventing Single Event Latchup with Deep P-Well on P-Substrate,'' Proceedings of International Reliability Physics Symposium (IRPS), June 2014.
[4]  R. Harada, S. Abe, H. Fuketa, T. Uemura, M. Hashimoto, and Y. Watanabe, ``Angular Dependency of Neutron Induced Multiple Cell Upsets in 65-Nm 10t Subthreshold Sram,'' IEEE Nuclear and Space Radiation Effects Conference, July 2012.
[5]  K. Watanabe, G. Fujita, T. Homemoto, and R. Hashimoto, ``A High-Speed H.264/AVC CABAC Decoder for 4K Video Utilizing Residual Data Accelerator,'' The 17th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2012), pp. 6-10, March 2012.
[6]  S. Abe, K. Shinkai, M. Hashimoto, and T. Onoye, ``Clock Skew Reduction by Self-Compensating Manufacturing Variability with On-Chip Sensors,'' In Proc. Great Lakes Symposium on VLSI (GLSVLSI), May 2010.
[7]  Yuki Kawamura, Yasutake Manabe, Takao Onoye, Kazuto Ohara, Hiroyuki Okada, and Ikuo Keshi, ``Implementation of Simultaneous Video Decoding on Multicore Processor,'' In Proc. of International Symposium on Communications, Control and Signal Processing (ISCCSP 2010), March 2010.
[8]  T. Enami, S. Ninomiya, K. Shinkai, S. Abe, and M. Hashimoto, ``Statistical Timing Analysis Considering Clock Jitter and Skew Due to Power Supply Noise and Process Variation,'' In Proc. International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pp. 41-46, March 2010.
[9]  S. Abe, K. Shinkai, M. Hashimoto, and T. Onoye, ``Clock Skew Reduction by Self-Compensating Manufacturing Variability with On-Chip Sensors,'' In Proc. International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), March 2010.
[10]  S. Watanabe, M. Hashimoto, and T. Sato, ``A Case for Exploiting Complex Arithmetic Circuits Towards Performance Yield Enhancement,'' In Proceedings of International Symposium on Quality Electronic Design (ISQED), pp. 401--407, March 2009.
[11]  S. Watanabe, M. Hashimoto, and T. Sato, ``Cascading Dependent Operations for Mitigating Timing Variability,'' In Proceedings. of Workshop on Quality-Aware Design (W-QUAD), June 2008.
[12]  S. Abe, M. Hashimoto, and T. Onoye, ``Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution,'' In Proc. International Symposium on Quality Electronic Design (ISQED), pp. 520-525, March 2008.
[13]  R. Hashimoto, T. Matsumura, Y. Nozato, K. Watanabe, and T. Onoye, ``Implementation of Object Attention Based on Multi-Agent Attractor Selection,'' In Proc. SISB, November 2007.
[14]  Yasutake Manabe, Junichi Hara, and Takao Onoye, ``Jpm-Based Differential Image Storage Scheme for Image Revision Management System,'' In IIEEJ Image Electronics and Visual Computing Workshop 2007, November 2007.
[15]  T. Kanamoto, Y. Ogasahara, K. Natsume, K. Yamaguchi, H. Amishiro, T. Watanabe, and M. Hashimoto, ``Impact of Well Edge Proximity Effect on Timing,'' In Proc. IEEE European Solid-State Device Research Conference, pp. 115-118, September 2007.
[16]  K. Watanabe, M. Ise, T. Onoye, H. Niwamoto, and I. Keshi, ``An Energy-Efficient Architecture of Wireless Home Network Based on Mac Broadcast and Transmission Power Control,'' In International Conference on Consumer Electronics Digest of Technical Papers, P1-20, January 2007.
[17]  K. Kawamoto, S. Mizuno, H. Abe, Y. Higuchi, S. Fujino, and I. Shirakawa, ``A Shingle Chip Automotive Control LSI Using SOI BiCDMOS,'' In in Proc. of 2000 International Conference on Solid State Device and Materials, pp. 486-487, August 2000.
[18]  T. Watanabe and N. Ishiura, ``Minimization of Spill Code Insertion by Register Constraint Analysis for Code Generation for Application Specific DSPs,'' In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2000), Pusan, Korea, pp. 953--956, July 2000.
[19]  N. Ishiura, T. Watanabe, and M. Yamaguchi, ``A Code Generation Method for Datapath Oriented Application Specific Processor Design,'' In in Proc. Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI 2000), pp. 71--78, April 2000.
研究会等発表論文
[1]  橋本 昌宜, 榎並 孝司, 新開 健一, 二宮 進有, 阿部 慎也, ``電源ノイズや製造ばらつきによるクロックジッタ・スキューを考慮した統計的タイミング解析,'' 情報処理学会DAシンポジウム, pp. 79-84, August 2009.
[2]  達可敏充, 橋本亮司, 渡邊賢治, 畠中理英, 尾上孝雄, ``ダイナミックスペクトルアクセスを用いたコグニティブ無線ネットワークにおけるノード位置推定手法の一検討,'' 信学技報, IN2008-220, vol. 108, no. 458, pp. 523-528, March 2009.
[3]  渡邊賢治, 達可敏充, 畠中理英, 尾上孝雄, ``屋内位置推定システムのための間取り推定に関する一検討,'' 信学技報, USN2008-33, vol. 108, no. 138, pp. 129-134, July 2008.
[4]  河村 侑輝, 真鍋 安武, 尾上 孝雄, 大原 一人, 岡田 浩行, 芥子 育雄, ``動画像並列復号のマルチコアプロセッサへの実装,'' 信学技報, SIS2008-23, vol. 108, no. 86, pp. 51-56, June 2008.
[5]  阿部 慎也, 橋本 昌宜, 尾上 孝雄, ``製造ばらつきを考慮したメッシュ型クロック分配網のスキュー評価,'' 情報処理学会DAシンポジウム, pp. 133-138, August 2007.
[6]  伊勢正尚, 小笠原泰弘, 渡邊賢治, 畠中理英, 尾上孝雄, 庭本浩明, 芥子育雄, 白川功, ``IEEE 802.15.4を用いたホームネットワーク向け無線ネットワークプロトコル,'' 信学技報, CAS2005-99, pp. 19--24, March 2006.
[7]  渡邊賢治, 伊勢正尚, 藤田玄, 畠中理英, 尾上孝雄, 庭本浩明, 芥子育雄, 白川功, ``無線ホームネットワークにおける消費電力および即時性の改善手法,'' 信学技報, CAS2005-100, pp. 25--30, March 2006.
[8]  渡辺 辰雄, 石浦 菜岐佐, ``特定用途向け DSP 用リターゲッタブルコンパイラによるデータパス指向協調設計手法,'' 信学技報, VLD2000-89, pp. 119--124, November 2000.
[9]  渡辺 辰雄, 石浦 菜岐佐, 山口 雅之, ``特定用途向け DSP のデータパス指向協調設計におけるコード生成手法,'' 信学会 第13回回路とシステム(軽井沢)ワークショップ, pp. 539--544, April 2000.
[10]  渡辺 辰雄, 石浦 菜岐佐, 山口 雅之, ``非直交なデータパスに対するリターゲッタブルコンパイラのスケジューリング手法,'' 信学会 第12回回路とシステム軽井沢ワークショップ, pp. 109--114, April 1999.
大会等発表論文
[1]  橋本亮司, 松村友哉, 野里良裕, 渡邊賢治, 尾上孝雄, ``複眼光学系による物体注視システムのハードウェア実現,'' 第9回 DSPS教育者会議 予稿集, pp. 87-88, August 2007.
[2]  阿部 慎也, 橋本 昌宜, 尾上 孝雄, ``メッシュ型クロック分配網のスキュー評価,'' 電子情報通信学会総合大会, A-3-5, March 2007.
[3]  渡邊 賢治, 西田 秀治, 藤田 玄, 尾上 孝雄, 白川 功, ``エージェント技術に基づくホームネットワーク制御システム,'' 電子情報通信学会ソサイエティ大会, A-1-30, September 2004.
[4]  渡辺 辰雄, 石浦 菜岐佐, ``特定用途向け DSP のコード生成におけるスピルコードの最小化,'' 信学会 ソサイエティ大会, A-3-20, October 2000.

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