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| T. Kouno, M. Hashimoto, and H. Onodera, "Input Capacitance Modeling of Logic Gates for Accurate Static Timing Analysis," In Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 453-456, November 2005. | |
| ID | 613 |
| 分類 | 国際会議 |
| タグ | |
| 表題 (title) |
Input Capacitance Modeling of Logic Gates for Accurate Static Timing Analysis |
| 表題 (英文) |
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| 著者名 (author) |
T. Kouno,M. Hashimoto,H. Onodera |
| 英文著者名 (author) |
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| 編者名 (editor) |
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| 編者名 (英文) |
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| キー (key) |
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| 書籍・会議録表題 (booktitle) |
Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC) |
| 書籍・会議録表題(英文) |
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| 巻数 (volume) |
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| 号数 (number) |
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| ページ範囲 (pages) |
453-456 |
| 組織名 (organization) |
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| 出版元 (publisher) |
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| 出版元 (英文) |
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| 出版社住所 (address) |
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| 刊行月 (month) |
11 |
| 出版年 (year) |
2005 |
| 採択率 (acceptance) |
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| URL |
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| 付加情報 (note) |
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| 注釈 (annote) |
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| 内容梗概 (abstract) |
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| 論文電子ファイル | 利用できません． |
| BiBTeXエントリ |
@inproceedings{id613,
title = {Input Capacitance Modeling of Logic Gates for Accurate Static Timing Analysis},
author = {T. Kouno and M. Hashimoto and H. Onodera},
booktitle = {Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC)},
pages = {453-456},
month = {11},
year = {2005},
}
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