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| K. Miyanohana, G. Fujita, K. Yanagida, T. Onoye, and I. Shirakawa, "Single Chip Implementation of Encoder-Decoder for Low Bit Rate Visural Communication," J. Circuits, Systems, and Computers, 7(5), pp. 441-457, May 1997. | |
| ID | 15 |
| 分類 | 論文誌 |
| タグ | |
| 表題 (title) |
Single Chip Implementation of Encoder-Decoder for Low Bit Rate Visural Communication |
| 表題 (英文) |
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| 著者名 (author) |
K. Miyanohana, G. Fujita, K. Yanagida, T. Onoye, I. Shirakawa |
| 英文著者名 (author) |
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| キー (key) |
Koji Miyanohana, Gen Fujita, Kazuhiro Yanagida, Takao Onoye, Isao Shirakawa |
| 定期刊行物名 (journal) |
J. Circuits, Systems, and Computers |
| 定期刊行物名 (英文) |
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| 巻数 (volume) |
7 |
| 号数 (number) |
5 |
| ページ範囲 (pages) |
441-457 |
| 刊行月 (month) |
5 |
| 出版年 (year) |
1997 |
| Impact Factor (JCR) |
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| URL |
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| 付加情報 (note) |
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| 注釈 (annote) |
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| 内容梗概 (abstract) |
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| 論文電子ファイル | 利用できません． |
| BiBTeXエントリ |
@article{id15,
title = {Single Chip Implementation of Encoder-Decoder for Low Bit Rate Visural Communication},
author = {K. Miyanohana and G. Fujita and K. Yanagida and T. Onoye and I. Shirakawa},
journal = {J. Circuits, Systems, and Computers},
volume = {7},
number = {5},
pages = {441-457},
month = {5},
year = {1997},
}
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