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分類 国際会議
著者名 (author) T. Kouno,M. Hashimoto,H. Onodera
英文著者名 (author)
編者名 (editor)
編者名 (英文)
キー (key)
表題 (title) Input Capacitance Modeling of Logic Gates for Accurate Static Timing Analysis
表題 (英文)
書籍・会議録表題 (booktitle) Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC)
書籍・会議録表題(英文)
巻数 (volume)
号数 (number)
ページ範囲 (pages) 453-456
組織名 (organization)
出版元 (publisher)
出版元 (英文)
出版社住所 (address)
刊行月 (month) November
出版年 (year) 2005
付加情報 (note)
注釈 (annote)
内容梗概 (abstract)
論文電子ファイル Not available.


[1-266]  T. Kouno, M. Hashimoto, and H. Onodera, ``Input Capacitance Modeling of Logic Gates for Accurate Static Timing Analysis,'' In Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 453-456, November 2005.

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    author = {T. Kouno and M. Hashimoto and H. Onodera},
    author_e = {},
    editor = {},
    editor_e = {},
    title = {Input Capacitance Modeling of Logic Gates for Accurate Static
    Timing Analysis},
    title_e = {},
    booktitle = {Proceedings of IEEE Asian Solid-State Circuits Conference (A-
    SSCC)},
    booktitle_e = {},
    volume = {},
    number = {},
    pages = {453-456},
    organization = {},
    publisher = {},
    publisher_e = {},
    address = {},
    month = {November},
    year = {2005},
    note = {},
    annote = {}
}

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