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分類 国際会議
著者名 (author) T. Yuasa,A. Tomita,T. Izumi,T. Onoye,Y. Nakamura
英文著者名 (author)
編者名 (editor)
編者名 (英文)
キー (key) , , , Takao Onoye, Yasuhisa Nakamura
表題 (title) An approach for circuit size reduction by variable reordering for PCA-chip2
表題 (英文)
書籍・会議録表題 (booktitle) Proc. Workshop on Synthesis and System Integration of Mixed Information Technologies
書籍・会議録表題(英文)
巻数 (volume)
号数 (number)
ページ範囲 (pages) 217--221
組織名 (organization)
出版元 (publisher)
出版元 (英文)
出版社住所 (address)
刊行月 (month) April
出版年 (year) 2003
付加情報 (note)
注釈 (annote)
内容梗概 (abstract)
論文電子ファイル Not available.


[1-159]  T. Yuasa, A. Tomita, T. Izumi, T. Onoye, and Y. Nakamura, ``An Approach for Circuit Size Reduction by Variable Reordering for Pca-Chip2,'' In Proc. Workshop on Synthesis and System Integration of Mixed Information Technologies, pp. 217--221, April 2003.

@inproceedings{1_159,
    author = {T. Yuasa and A. Tomita and T. Izumi and T. Onoye and Y. Nakamura},
    
    author_e = {},
    editor = {},
    editor_e = {},
    title = {An approach for circuit size reduction by variable reordering for
    PCA-chip2},
    title_e = {},
    booktitle = {Proc. Workshop on Synthesis and System Integration of Mixed
    Information Technologies},
    booktitle_e = {},
    volume = {},
    number = {},
    pages = {217--221},
    organization = {},
    publisher = {},
    publisher_e = {},
    address = {},
    month = {April},
    year = {2003},
    note = {},
    annote = {}
}

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