Search this article in Google Scholar


分類 国際会議
著者名 (author) T. Kanamoto,T. Ikeda,A. Tsuchiya,H. Onodera,M. Hashimoto
英文著者名 (author)
編者名 (editor)
編者名 (英文)
キー (key) Toshiki Kanamoto, Tatsuhiko Ikeda, Akira Tsuchiya, Hidetoshi Onodera, Masanori Hashimoto
表題 (title) Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in Soc Design
表題 (英文)
書籍・会議録表題 (booktitle) Proceedings of IEEE Wrokshop on Signal Propagation on Interconnects (SPI)
書籍・会議録表題(英文)
巻数 (volume)
号数 (number)
ページ範囲 (pages) 227--230
組織名 (organization)
出版元 (publisher)
出版元 (英文)
出版社住所 (address)
刊行月 (month) May
出版年 (year) 2006
付加情報 (note)
注釈 (annote)
内容梗概 (abstract)
論文電子ファイル Not available.


[1-156]  T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, and M. Hashimoto, ``Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in Soc Design,'' In Proceedings of IEEE Wrokshop on Signal Propagation on Interconnects (SPI), pp. 227--230, May 2006.

@inproceedings{1_156,
    author = {T. Kanamoto and T. Ikeda and A. Tsuchiya and H. Onodera and M.
    Hashimoto},
    author_e = {},
    editor = {},
    editor_e = {},
    title = {Si-Substrate Modeling Toward Substrate-Aware Interconnect
    Resistance and Inductance Extraction in Soc Design},
    title_e = {},
    booktitle = {Proceedings of IEEE Wrokshop on Signal Propagation on
    Interconnects (SPI)},
    booktitle_e = {},
    volume = {},
    number = {},
    pages = {227--230},
    organization = {},
    publisher = {},
    publisher_e = {},
    address = {},
    month = {May},
    year = {2006},
    note = {},
    annote = {}
}

This site is maintained by Onoye Lab.

PMAN 2.5.5 - Paper MANagement system / (C) 2002-2008, Osamu Mizuno / All rights reserved.