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分類 論文誌
著者名 (author) T. Uemura,T. Kato,H. Matsuyama,M. Hashimoto
英文著者名 (author)
キー (key)
表題 (title) Mitigating Multi-Bit-Upset with Well-Slits in 28 nm Multi-Bit-Latch
表題 (英文)
定期刊行物名 (journal) IEEE Transactions on Nuclear Science
定期刊行物名 (英文)
巻数 (volume) 60
号数 (number) 6
ページ範囲 (pages) 4362--4367
刊行月 (month) December
出版年 (year) 2013
付加情報 (note)
注釈 (annote)
内容梗概 (abstract)
論文電子ファイル Not available.


[0-152]  T. Uemura, T. Kato, H. Matsuyama, and M. Hashimoto, ``Mitigating Multi-Bit-Upset with Well-Slits in 28 Nm Multi-Bit-Latch,'' IEEE Transactions on Nuclear Science, vol. 60, no. 6, pp. 4362--4367, December 2013.

@article{0_152,
    author = {T. Uemura and T. Kato and H. Matsuyama and M. Hashimoto},
    author_e = {},
    title = {Mitigating Multi-Bit-Upset with Well-Slits in 28 nm Multi-Bit-Latch},
    
    title_e = {},
    journal = {IEEE Transactions on Nuclear Science},
    journal_e = {},
    volume = {60},
    number = {6},
    pages = {4362--4367},
    month = {December},
    year = {2013},
    note = {},
    annote = {}
}

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