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分類 論文誌
著者名 (author) T. Kanamoto,T. Ikeda,A. Tsuchiya,H. Onodera,M. Hashimoto
英文著者名 (author)
キー (key)
表題 (title) Si-substrate Modeling toward Substrate-aware Interconnect Resistance and Inductance Extraction in SoC Design
表題 (英文)
定期刊行物名 (journal) IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences
定期刊行物名 (英文)
巻数 (volume) E89-A
号数 (number) 12
ページ範囲 (pages) 3560-3568
刊行月 (month) December
出版年 (year) 2006
付加情報 (note)
注釈 (annote)
内容梗概 (abstract)
論文電子ファイル Not available.


[0-120]  T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, and M. Hashimoto, ``Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in Soc Design,'' IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E89-A, no. 12, pp. 3560-3568, December 2006.

@article{0_120,
    author = {T. Kanamoto and T. Ikeda and A. Tsuchiya and H. Onodera and M.
    Hashimoto},
    author_e = {},
    title = {Si-substrate Modeling toward Substrate-aware Interconnect
    Resistance and Inductance Extraction in SoC Design},
    title_e = {},
    journal = {IEICE Trans. on Fundamentals of Electronics, Communications and
    Computer Sciences},
    journal_e = {},
    volume = {E89-A},
    number = {12},
    pages = {3560-3568},
    month = {December},
    year = {2006},
    note = {},
    annote = {}
}

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