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| M. Hashimoto and H. Onodera, "Crosstalk Noise Optimization by Post-Layout Transistor Sizing," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, E87-A(12), pp. 3251-3257, December 2004. | |
| ID | 582 |
| 分類 | 論文誌 |
| タグ | |
| 表題 (title) |
Crosstalk Noise Optimization by Post-Layout Transistor Sizing |
| 表題 (英文) |
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| 著者名 (author) |
M. Hashimoto,H. Onodera |
| 英文著者名 (author) |
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| キー (key) |
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| 定期刊行物名 (journal) |
IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences |
| 定期刊行物名 (英文) |
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| 巻数 (volume) |
E87-A |
| 号数 (number) |
12 |
| ページ範囲 (pages) |
3251-3257 |
| 刊行月 (month) |
12 |
| 出版年 (year) |
2004 |
| Impact Factor (JCR) |
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| URL |
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| 付加情報 (note) |
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| 注釈 (annote) |
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| 内容梗概 (abstract) |
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| 論文電子ファイル | 利用できません． |
| BiBTeXエントリ |
@article{id582,
title = {Crosstalk Noise Optimization by Post-Layout Transistor Sizing},
author = {M. Hashimoto and H. Onodera},
journal = {IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences},
volume = {E87-A},
number = {12},
pages = {3251-3257},
month = {12},
year = {2004},
}
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