尾上研究室 研究業績一覧: H. Mizuno, H. Kobayashi, T. Onoye, and I. Shirakawa, Performance Estimation at Architecture Level for Embedded Systems, December 2002.
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H. Mizuno, H. Kobayashi, T. Onoye, and I. Shirakawa, "Performance Estimation at Architecture Level for Embedded Systems," IEEE Transaction on Fundamentals of Electronics, Communications and Computer Sciences, E85-A(12), pp. 2636--2644, December 2002.
ID 43
分類 論文誌
タグ
表題 (title) Performance Estimation at Architecture Level for Embedded Systems
表題 (英文) Performance Estimation at Architecture Level for Embedded Systems
著者名 (author) H. Mizuno, H. Kobayashi, T. Onoye, I. Shirakawa
英文著者名 (author) H. Mizuno, H. Kobayashi, T. Onoye, I. Shirakawa
キー (key) Hiroshi Mizuno, Hiroyuki Kobayashi, Takao Onoye, Isao Shirakawa
定期刊行物名 (journal) IEEE Transaction on Fundamentals of Electronics, Communications and Computer Sciences
定期刊行物名 (英文) IEEE Transaction on Fundamentals of Electronics, Communications and Computer Sciences
巻数 (volume) E85-A
号数 (number) 12
ページ範囲 (pages) 2636--2644
刊行月 (month) 12
出版年 (year) 2002
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BiBTeXエントリ
@article{id43,
         title = {Performance Estimation at Architecture Level for Embedded Systems},
        author = {H. Mizuno and  H. Kobayashi and  T. Onoye and  I. Shirakawa},
       journal = {IEEE Transaction on Fundamentals of Electronics, Communications and Computer Sciences},
        volume = {E85-A},
        number = {12},
         pages = {2636--2644},
         month = {12},
          year = {2002},
}
  

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