尾上研究室 研究業績一覧: Y. Ogasahara, T. Enami, M. Hashimoto, T. Sato, and T. Onoye, Validation of a Full-Chip Simulation Model for Supply Noise and Delay Dependence on Average Voltage Drop with On-Chip Delay Measurement, October 2007.
  • リスト
  •  表 
  • LaTeX
  • BibTeX
Detail of a work
Tweet
Y. Ogasahara, T. Enami, M. Hashimoto, T. Sato, and T. Onoye, "Validation of a Full-Chip Simulation Model for Supply Noise and Delay Dependence on Average Voltage Drop with On-Chip Delay Measurement," IEEE Trans. on Circuits and Systems—II: Express Briefs, 54(10), pp. 868-872, October 2007.
ID 426
分類 論文誌
タグ
表題 (title) Validation of a Full-Chip Simulation Model for Supply Noise and Delay Dependence on Average Voltage Drop with On-Chip Delay Measurement
表題 (英文)
著者名 (author) Y. Ogasahara,T. Enami,M. Hashimoto,T. Sato,T. Onoye
英文著者名 (author)
キー (key) Yasuhiro Ogasahara, Takashi Enami, Masanori Hashimoto, Takashi Sato, Takao Onoye
定期刊行物名 (journal) IEEE Trans. on Circuits and Systems—II: Express Briefs
定期刊行物名 (英文)
巻数 (volume) 54
号数 (number) 10
ページ範囲 (pages) 868-872
刊行月 (month) 10
出版年 (year) 2007
Impact Factor (JCR)
URL
付加情報 (note)
注釈 (annote)
内容梗概 (abstract)
論文電子ファイル 利用できません.
BiBTeXエントリ
@article{id426,
         title = {Validation of a Full-Chip Simulation Model for Supply Noise and Delay Dependence on Average Voltage Drop With On-Chip Delay Measurement},
        author = {Y. Ogasahara and T. Enami and M. Hashimoto and T. Sato and T. Onoye},
       journal = {IEEE Trans. on Circuits and Systems\—II: Express Briefs},
        volume = {54},
        number = {10},
         pages = {868-872},
         month = {10},
          year = {2007},
}
  

Search

Tags

1 件の該当がありました. : このページのURL : HTML

Language: 英語 | 日本語 || ログイン |

This site is maintained by Onoye Lab.
PMAN 3.2.10 build 20181029 - Paper MANagement system / (C) 2002-2016, Osamu Mizuno
Time to show this page: 0.024361 seconds.