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S. Yano and N. Ishiura, "Embedded Memory Array Testing Using a Scannable Configuration," IEICE Trans. Fundamentals of Electronics,Communications and Computer Sciences, E80-A(10), pp. 1934-1944, October 1997. | |
ID | 12 |
分類 | 論文誌 |
タグ | |
表題 (title) |
Embedded Memory Array Testing Using a Scannable Configuration |
表題 (英文) |
Embedded Memory Array Testing Using a Scannable Configuration |
著者名 (author) |
S. Yano, N. Ishiura |
英文著者名 (author) |
S. Yano, N. Ishiura |
キー (key) |
Seiken Yano, |
定期刊行物名 (journal) |
IEICE Trans.\ Fundamentals of Electronics,Communications and Computer Sciences |
定期刊行物名 (英文) |
IEICE Trans. Fundamentals of Electronics,Communications and Computer Sciences |
巻数 (volume) |
E80-A |
号数 (number) |
10 |
ページ範囲 (pages) |
1934-1944 |
刊行月 (month) |
10 |
出版年 (year) |
1997 |
Impact Factor (JCR) |
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URL |
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付加情報 (note) |
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注釈 (annote) |
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内容梗概 (abstract) |
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論文電子ファイル | 利用できません. |
BiBTeXエントリ |
@article{id12, title = {Embedded Memory Array Testing Using a Scannable Configuration}, author = {S. Yano and N. Ishiura}, journal = {IEICE Trans.\ Fundamentals of Electronics,Communications and Computer Sciences}, volume = {E80-A}, number = {10}, pages = {1934-1944}, month = {10}, year = {1997}, } |