論文誌

[1] Y. Ogasahara, M. Hashimoto, T. Kanamoto, and T. Onoye, "Supply Noise Suppression by Triple-Well Structure," IEEE Transactions on VLSI Systems, volume 21, number 4, pages 781--785, April 2013.

[2] Y. Ogasahara, M. Hashimoto, and T. Onoye, "All Digital Ring-Oscillator Based Macro for Sensing Dynamic Supply Noise Waveform," IEEE Journal of Solid-State Circuits, volume 44, number 6, pages 1745--1755, June 2009.

[3] T. Kanamoto, Y. Ogasahara, K. Natsume, K. Yamaguchi, H. Amishiro, T. Watanabe, and M. Hashimoto, "Impact of Well Edge Proximity Effect on Timing," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E91-A, number 12, pages 3461-3464, December 2008.

[4] Y. Ogasahara, M. Hashimoto, and T. Onoye, "Measurement and Analysis of Inductive Coupling Noise in 90nm Global Interconnects," IEEE Journal of Solid-State Circuits, volume 43, number 3, pages 718-728, March 2008.

[5] Y. Ogasahara, T. Enami, M. Hashimoto, T. Sato, and T. Onoye, "Validation of a Full-Chip Simulation Model for Supply Noise and Delay Dependence on Average Voltage Drop with On-Chip Delay Measurement," IEEE Trans. on Circuits and Systems—II: Express Briefs, volume 54, number 10, pages 868-872, October 2007.

[6] M. Ise, Y. Ogasahara, K. Watanabe, M. Hatanaka, T. Onoye, H. Niwamoto, I. Keshi, and I. Shirakawa, "Design and Implementation of Home Network Protocol for Appliance Control Based on IEEE 802.15.4," International Journal of Computer Science and Network Security, volume 7, number 7, pages 20-30, July 2007.

[7] Y. Ogasahara, M. Hashimoto, and T. Onoye, "Quantitative Prediction of On-Chip Capacitive and Inductive Crosstalk Noise　and Tradeoff between Wire Cross Sectional Area and Inductive Crosstalk Effect," In IEICE Trans. on Fundamentals of Electronics,　Communications and Computer Sciences, volume E90-A, number 4, pages 724--731, April 2007.

[8] M. Ise, Y. Ogasahara, T. Onoye, and I. Shirakawa, "W-CDMA Channel Codec by Configurable Processors," In Intelligent Automation and Soft Computing, volume 12, number 3, pages 317--29, 2006.

国際会議

[1] Y. Takai, Y. Ogasahara, M. Hashimoto, and T. Onoye, "Measurement of On-Chip I/O Power Supply Noise and Correlation Verification between Noise Magnitude and Delay Increase Due to Sso," In Proceedings of IEEE Workshop on Signal Propagation on Interconnects (SPI), pages 19--20, May 2010.

[2] Y. Ogasahara, M. Hashimoto, T. Kanamoto, and T. Onoye, "Measurement of Supply Noise Suppression by Substrate and Deep N-Well in 90nm Process," In Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC), pages 397--400, November 2008.

[3] Y. Ogasahara, M. Hashimoto, and T. Onoye, "Dynamic Supply Noise Measurement Circuit Composed of Standard Cells Suitable for In-Site Soc Power Integrity Verification," In Proc. IEEE/ACM Asia and South Pacific Design Automation Conference, pages 107-108, January 2008.

[4] Y. Ogasahara, M. Hashimoto, and T. Onoye, "Dynamic Supply Noise Measurement with All Digital Gated Oscillator for Evaluating Decoupling Capacitance Effect," In Proc. IEEE Custom Integrated Circuits Conference, pages 783-786, September 2007.

[5] T. Kanamoto, Y. Ogasahara, K. Natsume, K. Yamaguchi, H. Amishiro, T. Watanabe, and M. Hashimoto, "Impact of Well Edge Proximity Effect on Timing," In Proc. IEEE European Solid-State Device Research Conference, pages 115-118, September 2007.

[6] Y. Ogasahara, M. Hashimoto, and T. Onoye, "Quantitative Prediction of On-Chip Capacitive and Inductive Crosstalk Noise and Discussion on Wire Cross-Sectional Area Toward Inductive Crosstalk Free Interconnects," Proc. IEEE International Conference on Computer Design, pages 70--75, October 2006.

[7] Y. Ogasahara, M. Hashimoto, and T. Onoye, "Measurement of Inductive Coupling Effect on Timing in 90nm Global Interconnects," In Proc. IEEE Custom Integrated Circuits Conference, pages 721--724, September 2006.

[8] Y. Ogasahara, T. Enami, M. Hashimoto, T. Sato, and T. Onoye, "Measurement Results of Delay Degradation Due to Power Supply Noise Well Correlated with Full-Chip Simulation," In Proc.~IEEE Custom Integrated Circuits Conference, pages 861--864, September 2006.

[9] Y. Ogasahara, M. Hashimoto, and T. Onoye, "Measurement and Analysis of Delay Variation Due to Inductive Coupling," In Proc. IEEE Custom Integrated Circuits Conference, pages 305--308, September 2005.

[10] Y. Ogasahara, M. Ise, T. Onoye, and I. Shirakawa, "Architecture of Turbo Decoder for W-CDMA by Configurable Processor," In Proc.The 2004 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2004), Sendai, Japan, F2P-27-1--7F2P-27-4, page 7, July 2004.

[11] M. Ise, Y. Ogasahara, T. Onoye, and I. Shirakawa, "Implementation of W-CDMA Channel Codec by Configurable Processors," In Proc. Sixth Baiona Workshop on Signal Processing in Communications, pages 205--210, September 2003.