論文誌

[1] S. Iizuka, Y. Higuchi, M. Hashimoto, and T. Onoye, "Device-Parameter Estimation with Sensitivity-Configurable Ring Oscillator," IEICE Trans. Fundamentals of Electronics Communications and Computer Sciences, volume E98-A, number 12, pages 2607--2613, December 2015.

[2] T.T. Oo, T. Onoye, and K. Shin, "Partial Encryption Method That Enhances MP3 Security," IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, volume E98-A, number 8, pages 1760-1768, August 2015. [2.pdf]

[3] T. Shinada, M. Hashimoto, and T. Onoye, "Proximity Distance Estimation Based on Electric Field Communication between 1mm³ Sensor Nodes," Analog Integrated Circuits and Signal Processing, May 2015.

[4] S. Hirokawa, R. Harada, M. Hashimoto, and T. Onoye, "Characterizing Alpha- and Neutron-Induced Seu and Mcu on Sotb and Bulk 0.4-V Srams," IEEE Transactions on Nuclear Science, April 2015.

[5] H. Konoura, D. Alnajjar, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, K. Wakabayashi, M. Hashimoto, T. Onoye, and H. Onodera, "Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E97-A, number 12, pages 2518--2529, December 2014.

[6] T. Amaki, M. Hashimoto, and T. Onoye, "A Process and Temperature Tolerant Oscillator-Based True Random Number Generator," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E97-A, number 12, pages 2393--2399, December 2014.

[7] H. Konoura, T. Imagawa, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Comparative Evaluation of Lifetime Enhancement with Fault Avoidance on Dynamically Reconfigurable Devices," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E97-A, number 7, pages 1468--1482, July 2014.

[8] H. Konoura, T. Kameda, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Nbti Mitigation Method by Inputting Random Scan-In Vectors in Standby Time," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E97-A, number 7, pages 1483--1491, July 2014.

[9] R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Set Pulse-Width Measurement Suppressing Pulse-Width Modulation and Within-Die Process Variation Effects," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E97-A, number 7, pages 1461--1467, July 2014.

[10] H. Fuketa, R. Harada, M. Hashimoto, and T. Onoye, "Measurement and Analysis of Alpha-Particle-Induced Soft Errors and Multiple Cell Upsets in 10t Subthreshold Sram," IEEE Transactions on Device and Materials Reliability, volume 14, number 1, 463 -- 470, March 2014.

[11] D. Alnajjar, H. Konoura, Y. Ko, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Implementing Flexible Reliability in a Coarse Grained Reconfigurable Architecture," IEEE Transactions on VLSI Systems, volume 21, number 12, 2165 -- 2178, December 2013.

[12] K. Shinkai, M. Hashimoto, and T. Onoye, "A Gate-Delay Model Focusing on Current Fluctuation Over Wide Range of Process-Voltage-Temperature Variations," Integration, the VLSI Journal, volume 46, number 4, pages 345--358, September 2013.

[13] T.Kameda, H. Konoura, D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Field Slack Assessment for Predictive Fault Avoidance on Coarse-Grained Reconfigurable Devices," IEICE Trans. on Information and Systems , volume E96-D, number 8, pages 1624--1631, August 2013.

[14] T. Amaki, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "A Worst-Case-Aware Design Methodology for Noise-Tolerant Oscillator-Based True Random Number Generator with Stochastic Behavior Modeling," IEEE Transactions on Information Forensics and Security, volume 8, number 8, pages 1331--1342, August 2013.

[15] R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Impact of NBTI-Induced Pulse-Width Modulation on SET Pulse-Width Measurement," IEEE Transactions on Nuclear Science, volume 60, number 4, pages 2630--2634, August 2013.

[16] D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Pvt-Induced Timing Error Detection Through Replica Circuits and Time Redundancy in Reconfigurable Devices," IEICE Electronics Express (ELEX), volume 10, number 5, April 2013.

[17] Y. Ogasahara, M. Hashimoto, T. Kanamoto, and T. Onoye, "Supply Noise Suppression by Triple-Well Structure," IEEE Transactions on VLSI Systems, volume 21, number 4, pages 781--785, April 2013.

[18] I. Homjakovs, T. Hirose, Y. Osaki, M. Hashimoto, and T. Onoye, "A 0.8-V 110-Na Cmos Current Reference Circuit Using Subthreshold Operation," IEICE Electronics Express (ELEX), volume 10, number 4, March 2013.

[19] T. Amaki, M. Hashimoto, and T. Onoye, "Jitter Amplifier for Oscillator-Based True Random Number Generator," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E96-A, number 3, pages 684--696, March 2013.

[20] I. Homjakovs, M. Hashimoto, T. Hirose, and T. Onoye, "Signal-Dependent Analog-To-Digital Conversion Based on Minimax Sampling," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E96-A, number 2, pages 459--468, February 2013.

[21] M. Hatanaka, T. Homemoto, and T. Onoye, "Architecture and Implementation of Fading Compensation for Dynamic Spectrum Access Wireless Communication Systems," VLSI Design, volume vol. 2013, Article ID 967370, 9 pages, 2013.

[22] Y. Takai, M. Hashimoto, and T. Onoye, "Power Gating Implementation for Supply Noise Mitigation with Body-Tied Triple-Well Structure," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E95-A, number 12, pages 2220--2225, December 2012.

[23] S. Kimura, M. Hashimoto, and T. Onoye, "A Body Bias Clustering Method for Low Test-Cost Post-Silicon Tuning," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E95-A, number 12, pages 2292--2300, December 2012.

[24] M. Okada, T. Onoye, and W. Kobayashi, "A Ray Tracing Simulation of Sound Diffraction Based on the Analytic Secondary Source Model," IEEE Trans. Audio, Speech and Language Processing , volume 20, number 9, 2448-2460 , November 2012.

[25] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Adaptive Performance Compensation with In-Situ Timing Error Predictive Sensors for Subthreshold Circuits," IEEE Transactions on VLSI Systems, volume 20, number 2, pages 333--343, February 2012.

[26] H. Konoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Stress Probability Computation for Estimating NBTI-Induced Delay Degradation," IEICE Trans. Fundamentals, volume E94-A, number 12, pages 2545-2553, December 2011.

[27] K. Shinkai, M. Hashimoto, and T. Onoye, "Extracting Device-Parameter Variations with Ro-Based Sensors," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E94-A, number 12, pages 2537--2544, December 2011.

[28] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Neutron-Induced Soft Errors and Multiple Cell Upsets in 65-Nm 10t Subthreshold Sram," IEEE Transactions on Nuclear Science, volume 58, number 4, pages 2097--2102, August 2011.

[29] H. Fuketa, D. Kuroda, M. Hashimoto, and T. Onoye, "An Average-Performance-Oriented Subthreshold Processor Self-Timed by Memory Read Completion," IEEE Transactions on Circuits and Systems II, volume 58, number 5, pages 299--303, May 2011.

[30] R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Measurement Circuits for Acquiring SET Pulse Width Distribution with Sub-FO1-inverter-delay Resolution," IEICE Transaction on Fundamentals of Electronics, Communications and Computer Sciences, volume E93-A, number 12, pages 2417-2423, December 2010. [2.pdf]

[31] M. Okada, N. Iwanaga, T. Matsumura, T. Onoye, and W. Kobayashi, "3D Sound Rendering for Multiple Sound Sources Based on Fuzzy Clustering," IEICE Trans. Fundamentals, volume E93-A, number 11, pages 2163-2172, November 2010.

[32] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Transistor Variability Modeling and Its Validation with Ring-Oscillation Frequencies for Body-Biased Subthreshold Circuits," IEEE Transactions on VLSI Systems, volume 18, number 7, pages 1118--1129, July 2010.

[33] K. Shinkai, M. Hashimoto, and T. Onoye, "Prediction of Self-Heating in Short Intra-Block Wires," IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, volume E93-A, number 3, pages 583-594, March 2010. [2.pdf]

[34] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction," IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, volume E92-A, number 12, pages 3094-3102, December 2009.

[35] Y. Ogasahara, M. Hashimoto, and T. Onoye, "All Digital Ring-Oscillator Based Macro for Sensing Dynamic Supply Noise Waveform," IEEE Journal of Solid-State Circuits, volume 44, number 6, pages 1745--1755, June 2009.

[36] K. Hamamoto, H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "An Experimental Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability," IEICE Trans. on Electronics, volume E92-C, number 2, pages 281-285, February 2009.

[37] S. Abe, M. Hashimoto, and T. Onoye, "Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E91-A, number 12, pages 3481-3487, December 2008.

[38] R. Hashimoto, T. Matsumura, Y. Nozato, K. Watanabe, and T. Onoye, "Implementation of Multi-Agent Object Attention System Based on Biologically Inspired Attractor Selection," IEICE Trans. Fundamentals, volume E91-A, number 10, October 2008.

[39] Y. Ogasahara, M. Hashimoto, and T. Onoye, "Measurement and Analysis of Inductive Coupling Noise in 90nm Global Interconnects," IEEE Journal of Solid-State Circuits, volume 43, number 3, pages 718-728, March 2008.

[40] Y. Ogasahara, T. Enami, M. Hashimoto, T. Sato, and T. Onoye, "Validation of a Full-Chip Simulation Model for Supply Noise and Delay Dependence on Average Voltage Drop with On-Chip Delay Measurement," IEEE Trans. on Circuits and Systems—II: Express Briefs, volume 54, number 10, pages 868-872, October 2007.

[41] M. Ise, Y. Ogasahara, K. Watanabe, M. Hatanaka, T. Onoye, H. Niwamoto, I. Keshi, and I. Shirakawa, "Design and Implementation of Home Network Protocol for Appliance Control Based on IEEE 802.15.4," International Journal of Computer Science and Network Security, volume 7, number 7, pages 20-30, July 2007.

[42] K. Tsujino, W. Kobayashi, T. Onoye, and Y. Nakamura, "Automatic Filter Design for 3-D Sound Movement in Embedded Applications," In Acoustical Science and Technology, volume 28, number 4, pages 219-229, July 2007.

[43] Y. Ogasahara, M. Hashimoto, and T. Onoye, "Quantitative Prediction of On-Chip Capacitive and Inductive Crosstalk Noise　and Tradeoff between Wire Cross Sectional Area and Inductive Crosstalk Effect," In IEICE Trans. on Fundamentals of Electronics,　Communications and Computer Sciences, volume E90-A, number 4, pages 724--731, April 2007.

[44] K. Tsujino, W. Kobayashi, T. Onoye, and Y. Nakamura, "Efficient 3-D Sound Movement with Time-Varying Iir Filters," In IEICE Trans. Fundamentals, volume E90-A, number 3, pages 618--625, March 2007.

[45] K. Watanabe, M. Ise, T. Onoye, H. Niwamoto, and I. Keshi, "An Energy-Efficient Architecture of Wireless Home Network Based on Mac Broadcast and Transmission Power Control," In IEEE Trans. Consumer Electronics, volume 53, number 1, pages 124--130, February 2007.

[46] G. Fujita, T. Imanaka, H. V. Nhat, T. Onoye, and I. Shirakawa, "Real-Time Human Object Extraction Method for Mobile Systems Based on Color Space Segmentation," In IEICE Trans. Fundamentals, volume E89-A, number 4, pages 941--949, April 2006.

[47] H. Tsutsui, T. Masuzaki, Y. Hayashi, Y. Taki, T. Izumi, T. Onoye, and Y. Nakamura, "Design Framework for JPEG2000 System Architecture," In Journal of Intelligent Automation and Soft Computing, volume 13, number 3, pages 331--343, March 2006.

[48] Z. Guo, Y. Nishikawa, R. Y. Omaki, T. Onoye, and I. Shirakawa, "A Low-Complexity FEC Assignment Scheme for Motion JPEG2000 Over Wireless Network," IEEE Transactions on Consumer Electronics, volume 52, number 1, pages 81--86, February 2006.

[49] M. Ise, Y. Ogasahara, T. Onoye, and I. Shirakawa, "W-CDMA Channel Codec by Configurable Processors," In Intelligent Automation and Soft Computing, volume 12, number 3, pages 317--29, 2006.

[50] A. Kosaka, H. Okuhata, T. Onoye, and I. Shirawaka, "Desing of Ogg Vorbis Decoder System for Embedded Platform," IEICE Trans. Fundamentals, volume E88-A, number 8, pages 2124--2130, August 2005.

[51] K. Tsujino, K. Furuya, W. Kobayashi, T. Izumi, T. Onoye, and Y. Nakamura, "Design of Realtime 3-D Sound Processing System," In IEICE Trans. Fundamentals, volume E88-A, number 8, pages 2124--2130, August 2005.

[52] Y. Mitsuyama, M. Kimura, T. Onoye, and I. Shirakawa, "Architecture of IEEE802.11i Cipher Algorithms for Embedded Systems," IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, volume E88-A, number 4, pages 899-906, April 2005.

[53] T. Matsumura, N. Iwanaga, W. Kobayashi, T. Onoye, and I. Shirakawa, "Embedded 3D Sound Movement System Based on Feature Extraction of Head-Related Transfer Function," IEEE Transactions on Consumer Electronics, volume 51, number 1, pages 262--267, February 2005.

[54] M. Kimura, M. H. Miki, T. Onoye, and I. Shirakawa, "Implementation of Java Accelerator for High-Performance Embedded Systems," in IEICE Trans. Fundamentals, volume E86-A, number 12, pages 3079--3088, December 2003.

[55] N. Iwanaga, W. Kobayashi, K. Furuya, T. Onoye, and I. Shirakawa, "Embedded Implementation of Acoustic Field Enhancement for Stereo Sound Sources," in IEEE Trans. on Consumer Electronics, volume 49, number 3, pages 737--741, August 2003.

[56] T. Okamoto, T. Yuasa, T. Izumi, T. Onoye, and Y. Nakamura, "Design Tools and Trial Design for Pca-Chip2," In IEICE Trans. Information and Systems,, volume E86-D, number 5, pages 868--871, May 2003.

[57] K. Nakagawa, M. Kawakita, K. Sato, M. Minakuchi, T. Onoye, T. Chiba, and I. Shirakawa, "Object Sharing Scheme for Heterogeneous Environment," in IEICE Transaction on Fundamentals of Electronics, Communications and Computer Sciences, volume E86-A, number 4, pages 813--821, April 2003.

[58] N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa, "Single DSP Implementation of Realtime 3D Sound Synthesis Algorithm," Journal of Circuits, Systems and Computers, volume 12, number 1, pages 55-73, February 2003.

[59] H. Mizuno, H. Kobayashi, T. Onoye, and I. Shirakawa, "Performance Estimation at Architecture Level for Embedded Systems," IEEE Transaction on Fundamentals of Electronics, Communications and Computer Sciences, volume E85-A, number 12, pages 2636--2644, December 2002.

[60] Y. Ohtani, N. Kawahara, H. Nakaoka, T. Tomaru K. Maruyama, T. Chiba, T. Onoye, and I. Shirakawa, "Wireless Digital Video Transmission System Using IEEE802.11b PHY with Error Correction Block Based ARQ Protocol," IEICE (Institute of Electronics, Information and Communication Engineers) Transaction on Communications, volume E85-B, number 10, pages 2032--2043, October 2002.

[61] H. Okada, A.-E. Shiitev, H.-S. Song, G. Fujita, T. Onoye, and I. Shirakawa, "Error Detection by Digital Watermarking for MPEG-4 Video Coding," IEICE (Institute of Electronics, Information and Communication Engineers) Transaction on Fundamentals of Electronics, Communications and Computer Sciences, volume E85-A, number 6, pages 1281--1288, June 2002.

[62] W. Kobayashi, N. Sakamoto, T. Onoye, and I. Shirakawa, "3D Acoustic Image Localization Algorithm by Embedded DSP," IEICE(The Institute of Electronics, Information and Communication Engineers) Trans. Fundamentals of Electronics Communications and Computer Sciences, volume E84-A, number 6, pages 1423--1430, June 2001.

[63] Z. Andales, Y. Mitsuyama, T. Onoye, and I. Shirakawa, "A Novel Dynamically Reconfigurable Hardware-Based Cipher," 情報処理学会論文誌, volume 42, number 4, pages 958--966, April 2001.

[64] B.Y. Song, M. Furuie, Y. Yoshida, T. Onoye, and I. Shirakawa, "Low-Power VLSI Implementation by NMOS 4-Phase Dynamic Logic," Trans. of IPSJ, volume 41, number 4, pages 899--907, April 2000.

[65] M. Hatanaka, T. Masaki, T. Onoye, and K. Murakami, "VLSI Architecture of Switching Control for AAL Type2 Switch," IEICE Trans. Fundamentals, volume E83--A, number 3, pages 435--441, March 2000.

[66] B.Y. Song, M. Furuie, Y. Yoshida, T. Onoye, and I. Shirakawa, "Low-Power Scheme of NMOS 4-Phase Dynamic Logic," IEICE Trans. Electron., volume E82--C, number 9, pages 1772--1776, September 1999.

[67] H. Fujisima, Y. Takemoto, T. Onoye, and I. Shirakawa, "An Architecture of a Matrix-Vector Multiplier Dedicated to Video Decoding and Three-Dimensional Computer Graphics," IEEE Trans. Circuits and Systems for Video Technology, volume 9, number 2, pages 306--314, March 1999.

[68] H. Okuhata, Morgan H. Miki, T. Onoye, and I. Shirakawa, "A Low-Power DSP Core Architecture for Low Bitrate Speech Codec," IEICE Trans. Fundamentals, volume E81-C, number 8, pages 1616--1621, August 1998.

[69] G. Fujita, T. Onoye, and I. Shirakawa, "A VLSI Architecture for Motion Estimation Core Dedicated to H.263 Video Coding," IEICE Trans. Electronics, volume E81-C, number 5, pages 702--707, May 1998.

[70] T. Masaki, Y. Nakatani, T. Onoye, N. Yamai, and K. Murakami, "Voice Communication on Multimedia ATM Network Using Shared VCI Cell," IEICE Trans. Communications, volume E81-B, number 2, pages 340-346, February 1998.

[71] K. Miyanohana, G. Fujita, K. Yanagida, T. Onoye, and I. Shirakawa, "Single Chip Implementation of Encoder-Decoder for Low Bit Rate Visural Communication," J. Circuits, Systems, and Computers, volume 7, number 5, pages 441-457, May 1997.

[72] T. Masaki, Y. Nakatani, T. Onoye, and K. Murakami, "Voice and Telephony Over ATM for Multimedia Network Using Shared VCI Cell," J. Circuits, Systems, and Computers, volume 7, number 2, pages 93-110, April 1997.

[73] T. Onoye, G. Fujita, M. Takatsu, I. Shirakawa, and N. Yamai, "Single Chip Implementation of Motion Estimator Dedicated to MPEG2 MP@HL," in Proc. IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, volume E79-A, number 8, pages 1210-1216, August 1996.

国際会議

[1] R. Shirai, Y. Itoh, T. Fukamachi, M. Yamashita, and T. Onoye, "Optrod: Operating Multiple Various Actuators Simultaneously by Projected Images," In SIGGRAPH Asia 2017 Emerging Technologies, number 11, pages 1-2, November 2017.

[2] Y. Masuda, M. Hashimoto, and T. Onoye, "Measurement of Timing Error Detection Performance of Software-Based Error Detection Mechanisms and Its Correlation with Simulation," In ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pages 28-35, March 2016.

[3] Y. Masuda, M. Hashimoto, and T. Onoye, "Performance Evaluation of Software-Based Error Detection Mechanisms for Localizing Electrical Timing Failures under Dynamic Supply Noise," In Proceedings of International Conference on Computer-Aided Design (ICCAD), pages 315-322, November 2015.

[4] R. Doi, M. Hashimoto, and T. Onoye, "An Analytic Evaluation on Soft Error Immunity Enhancement Due to Temporal Triplication," IEEE Pacific Rim International Symposium on Dependable Computing (PRDC), November 2015.

[5] E. Aliwarga, J. Yu, M. Hatanaka, and T. Onoye, "Design of Generic Hardware for Soft Cascade-Based Linear Svm Classification," In International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), pages 257-262, November 2015.

[6] S. Iizuka, Y. Masuda, M. Hashimoto, and T. Onoye, "Stochastic Timing Error Rate Estimation under Process and Temporal Variations," In Proceedings of International Test Conference (ITC), October 2015.

[7] M. Ueno, M. Hashimoto, and T. Onoye, "Real-Time On-Chip Supply Voltage Sensor and Its Application to Trace-Based Timing Error Localization," Proceedings of International On-Line Testing Symposium (IOLTS), pages 188--193, July 2015.

[8] S. Ukawa, T. Shinada, M. Hashimoto, Y. Itoh, and T. Onoye, "3d Node Localization from Node-To-Node Distance Information Using Cross-Entropy Method," Proceedings of Virtual Reality Conference (VR), March 2015.

[9] S. Iizuka, Y. Higuchi, M. Hashimoto, and T. Onoye, "Area Efficient Device-Parameter Estimation Using Sensitivity-Configurable Ring Oscillator," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 731--736, January 2015.

[10] M. Hashimoto, D. Alnajjar, H. Konoura, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, K. Wakabayashi, T. Onoye, and H. Onodera, "Reliability-Configurable Mixed-Grained Reconfigurable Array Compatible with High-Level Synthesis," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 14--15, January 2015.

[11] T. Amaki, M. Hashimoto, and T. Onoye, "An Oscillator-Based True Random Number Generator with Process and Temperature Tolerance," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 4--5, January 2015.

[12] A. Iokibe, M. Hashimoto, and T. Onoye, "Feasibility Evaluation on an Instant Invader Detection System with Ultrasonic Sensors Scattered on the Ground," Proceedings of International Conference on Sensing Technology (ICST), pages 188--193, September 2014.

[13] M. Ueno, M. Hashimoto, and T. Onoye, "Trace-Based Fault Localization with Supply Voltage Sensor," ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), March 2014.

[14] D. Alnajjar, H. Konoura, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, S. Noda, K. Wakabayashi, M. Hashimoto, T. Onoye, and H. Onodera, "Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-To-Array Mapping and Its Radiation Testing," In Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC), pages 313-316, November 2013.

[15] T. Amaki, M. Hashimoto, and T. Onoye, "A Process and Temperature Tolerant Oscillator-Based True Random Number Generator with Dynamic 0/1 Bias Correction," In Proceedings of Asian Solid-State Circuits Conference (A-SSCC), pages 133-136, November 2013.

[16] S. Iizuka, M. Mizuno, D. Kuroda, M. Hashimoto, and T. Onoye, "Stochastic Error Rate Estimation for Adaptive Speed Control with Field Delay Testing," In Proc. International Conference on Computer-Aided Design (ICCAD), pages 107-114, November 2013.

[17] J. Kono, M. Hashimoto, and T. Onoye, "Feasibility Evaluation of Near-Field Communication in Clay with 1-Mm^3 Antenna," Proceedings of Asia-Pacific Microwave Conference (APMC), pages 1121--1123, November 2013.

[18] R. Harada, M. Hashimoto, and T. Onoye, "Nbti Characterization Using Pulse-Width Modulation," IEEE/ACM Workshop on Variability Modeling and Characterization, November 2013.

[19] Y.Fukuhara, A.Yamada, and T.Onoye, "An Image Compression Method for Frame Memory Size Reduction Using Local Feature of Images," In The 18th Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2013), pages 288-289, October 2013.

[20] T. Shinada, M. Hashimoto, and T. Onoye, "Proximity Distance Estimation Based on Capacitive Coupling between 1mm^3 Sensor Nodes," Proceedings of International NEWCAS Conference, June 2013.

[21] M. Ueno, M. Hashimoto, and T. Onoye, "Real-Time Supply Voltage Sensor for Detecting/Debugging Electrical Timing Failures," Proceedings of Reconfigurable Architectures Workshop (RAW), pages 301--305, May 2013.

[22] D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Static Voltage Over-Scaling and Dynamic Voltage Variation Tolerance with Replica Circuits and Time Redundancy in Reconfigurable Devices," Proceedings of International Conference on ReConFigurable Computing and FPGAs (ReConFig), December 2012.

[23] I. Homjakovs, M. Hashimoto, T. Hirose, and T. Onoye, "Signal-Dependent Analog-To-Digital Converter Based on Minimax Sampling," Proceedings of International SoC Design Conference (ISOCC), 120 -- 123 , November 2012.

[24] R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Impact of Nbti-­Induced Pulse-Width Modulation on Set Pulse-Width Measurement," Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS), September 2012.

[25] T. Kameda, H. Konoura, D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "A Predictive Delay Fault Avoidance Scheme for Coarse-Grained Reconfigurable Architecture," Proceedings of International Conference on Field Programmable Logic and Applications (FPL) , August 2012.

[26] R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Set Pulse-Width Measurement Eliminating Pulse-Width Modulation and Within-Die Process Variation Effects," Proceedings of International Reliability Physics Symposium (IRPS), April 2012.

[27] S. Kimura, M. Hashimoto, and T. Onoye, "Body Bias Clustering for Low Test-Cost Post-Silicon Tuning," In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 283--289, February 2012.

[28] H. Konoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Implications of Reliability Enhancement Achieved by Fault Avoidance on Dynamically Reconfigurable Architectures," In Proc. 21st International Conference on Field Programmable Logic and Applications (FPL2011), Chania, Crete, Greece, pages 189-194, September 2011.

[29] Y. Takai, M. Hashimoto, and T. Onoye, "Power Gating Implementation for Noise Mitigation with Body-Tied Triple-Well Structure," In Proceedings of IEEE Custom Integrated Circuits Conference (CICC), September 2011.

[30] M. Okada, T. Onoye, and W. Kobayashi, "A Ray Tracing Simulation of Sound Diffraction Based on Analytic Secondary Source Model," In 19th European Signal Processing Conference (EUSIPCO-2011), Barcelona, Spain, pages 1653-1657, August 2011.

[31] I. Homjakovs, M. Hashimoto, T. Hirose, and T. Onoye, "Signal-Dependent Analog-To-Digital Conversion Based on Minimax Sampling," In Proceedings of International Midwest Symposium on Circuits and Systems (MWSCAS), August 2011.

[32] T. Amaki, M. Hashimoto, and T. Onoye, "An Oscillator-Based True Random Number Generator with Jitter Amplifier," In Proc. IEEE International Symposium on Circuits and Systems (ISCAS 2011), pages 725-728, May 2011.

[33] R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Neutron Induced Single Event Multiple Transients with Voltage Scaling and Body Biasing," In Proc. International Reliability Physics Symposium (IRPS), April 2011.

[34] S. Kimura, M. Hashimoto, and T. Onoye, "Body Bias Clustering for Low Test-Cost Post-Silicon Tuning," In ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pages 46--51, April 2011.

[35] K. Shinkai, M. Hashimoto, and T. Onoye, "Extracting Device-Parameter Variations with Ro-Based Sensors," In ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pages 13--18, March 2011.

[36] D. Alnajjar, H. Kounoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Mttf Measurement under Alpha Particle Radiation in a Coarse-Grained Reconfigurable Architecture with Flexible Reliability," In IEEE Workshop on Silicon Errors in Logic - System Effects, March 2011.

[37] T. Amaki, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "A Design Procedure for Oscillator-Based Hardware Random Number Generator with Stochastic Behavior Modeling," In Proc. International Workshop on Information Security Applications (WISA 2010), pages 107-121, January 2011.

[38] T. Amaki, M. Hashimoto, and T. Onoye, "Jitter Amplifier for Oscillator-Based True Random Number Generator," In Proc. Asia and South Pacific Design Automation Conference (ASP-DAC 2011), pages 81-82, January 2011.

[39] M. Hatanaka, R. Hashimoto, T. Tatsuka, T. Onoye, H. Hatamoto, S. Ibi, S. Miyamoto, and S. Sampei, "VLSI Design of OFDM Baseband Transceiver with Dynamic Spectrum Access," In Proc. of the 18th International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS2010), pages 329-332, December 2010.

[40] Y. Takai, M. Hashimoto, and T. Onoye, "Evaluation of Power Gating Structures Focusing on Power Supply Noise with Measurement and Simulation," In Proceedings of IEEE Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), pages 213--216, October 2010.

[41] L. M. Handaya, M. Okada, T. Onoye, and W. Kobayashi, "Improvement of Frontal Localization with Complement of Multiple Delayed Sounds," 2010 International Workshop on Information Communication Technology, August 2010.

[42] S. Abe, K. Shinkai, M. Hashimoto, and T. Onoye, "Clock Skew Reduction by Self-Compensating Manufacturing Variability with On-Chip Sensors," In Proc. Great Lakes Symposium on VLSI (GLSVLSI), May 2010.

[43] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Alpha-Particle-Induced Soft Errors and Multiple Cell Upsets in 65-Nm 10t Subthreshold Sram," In Proceedings of International Reliability Physics Symposium (IRPS), pages 213--217, May 2010.

[44] Y. Takai, Y. Ogasahara, M. Hashimoto, and T. Onoye, "Measurement of On-Chip I/O Power Supply Noise and Correlation Verification between Noise Magnitude and Delay Increase Due to Sso," In Proceedings of IEEE Workshop on Signal Propagation on Interconnects (SPI), pages 19--20, May 2010.

[45] D. Kuroda, H. Fuketa, M. Hashimoto, and T. Onoye, "A 16-Bit Risc Processor with 4.18pj/Cycle at 0.5v Operation," In Proceedings of IEEE COOL Chips, page 190, April 2010.

[46] H. Konoura, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Comparative Study on Delay Degrading Estimation Due to Nbti with Circuit/Instance/Transistor-Level Stress Probability Consideration," In Proc. International Symposium on Quality Electronic Design (ISQED), pages 646-651, March 2010.

[47] R. Harada, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Measurement Circuits for Acquiring SET Pulse Width Distribution with Sub-FO1-inverter-delay Resolution," In Proc. International Symposium on Quality Electronic Design (ISQED), March 2010. [2.pdf]

[48] S. Abe, K. Shinkai, M. Hashimoto, and T. Onoye, "Clock Skew Reduction by Self-Compensating Manufacturing Variability with On-Chip Sensors," In Proc. International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), March 2010.

[49] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Adaptive Performance Control with Embedded Timing Error Predictive Sensors for Subthreshold Circuits," In Proc. Asia and South Pacific Design Automation Conference (ASP-DAC), pages 361-362, January 2010.

[50] D. Alnajjar, Y. Ko, T. Imagawa, M. Hiromoto, Y. Mitsuyama, M. Hashimoto, H. Ochi, and T. Onoye, "Soft Error Resilient Vlsi Architecture for Signal Processing," In Proceedings of IEEE International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), pages 183--186, December 2009.

[51] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Adaptive Performance Compensation with In-Situ Timing Error Prediction for Subthreshold Circuits," In Proc. IEEE Custom Integrated Circuits Conference, pages 215-218, September 2009.

[52] R. Hashimoto, T. Tatsuka, M. Hatanaka, T. Onoye, H. Hatamoto, S. Ibi, S. Miyamoto, and S. Sampei, "Implementation of Ofdm Baseband Transceiver with Dynamic Spectrum Access for Cognitive Radio Systems," In Proc. of 9th International Symposium on Communication and Information Technology (ISCIT2009), pages 658-663, September 2009.

[53] K. Hamamoto, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Tuning-Friendly Body Bias Clustering for Compensating Random Variability in Subthreshold Circuits," In Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), pages 51--56, August 2009.

[54] D. Alnajjar, Y. Ko, T. Imagawa, H. Konoura, M. Hiromoto, Y. Mitsuyama, M. Hashimoto, H. Ochi, and T. Onoye, "Coarse-Grained Dynamically Reconfigurable Architecture with Flexible Reliability," In Proceedings of International Conference on Field Programmable Logic and Applications (FPL), pages 186--192, August 2009.

[55] M. Okada, N. Iwanaga, T. Matsumura, T. Onoye, and W. Kobayashi, "An Embedded Sound Localization System for Multiple Sources by Fuzzy Clustering with Spatial Constraints," In 2009 International Workshop on Nonlinear Circuits and Signal Processing (NCSP '09), Waikiki, Hawaii, pages 257-260, March 2009.

[56] Y. Ko, D. Alnajjar, Y. Mitsuyama, M. Hashimoto, and T. Onoye, "Coarse-Grained Dynamically Reconfigurable Architecture with Flexible Reliability," In Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pages 236--241, March 2009.

[57] D. Alnajjar, Y. Ko, T. Imagawa, M. Hiromoto, Y. Mitsuyama, M. Hashimoto, H. Ochi, and T. Onoye, "A Coarse-Grained Dynamically Reconfigurable Architecture Enabling Flexible Reliability," In Proceedings of IEEE Workshop on System Effects of Logic Soft Errors (SELSE), March 2009.

[58] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction," In Proc. Asia and South Pacific Design Automation Conference (ASP-DAC), pages 266-271, January 2009.

[59] M. Okada, N. Iwanaga, T. Matsumura, T. Onoye, and W. Kobayashi, "A 3D Sound Localization Method for Multiple Sound Sources Based on Fuzzy Clustering," In 2008 International Workshop on Smart Info-Media Systems in Bangkok (SISB 2008), pages 133-138, December 2008.

[60] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Vth Variation Modeling and Its Validation with Ring Oscillation Frequencies for Body-Biased Circuits and Subthreshold Circuits," In ICCAD Colocated Workshop on Test Structure Design for Variability Characterization, November 2008.

[61] Y. Ogasahara, M. Hashimoto, T. Kanamoto, and T. Onoye, "Measurement of Supply Noise Suppression by Substrate and Deep N-Well in 90nm Process," In Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC), pages 397--400, November 2008.

[62] H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Correlation Verification between Transistor Variability Model with Body Biasing and Ring Oscillation Frequency in 90nm Subthreshold Circuits," In Proc. IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), pages 3-8, August 2008.

[63] K. Hamamoto, H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Experimental Study on Body-Biasing Layout Style - Negligible Area Overhead Enables Sufficient Speed Controllability -," In ACM Great Lakes Symposium on VLSI, pages 387-390, May 2008.

[64] S. Abe, M. Hashimoto, and T. Onoye, "Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution," In Proc. International Symposium on Quality Electronic Design (ISQED), pages 520-525, March 2008.

[65] H. Okuhata, K. Takahashi, Y. Nozato, T. Onoye, and I. Shirakawa, "Video Image Enhancement Scheme for High Resolution Consumer Devices," In Proc. of International Symposium on Communications, Control and Signal Processing (ISCCSP2008), pages 639-644, March 2008.

[66] Y. Ogasahara, M. Hashimoto, and T. Onoye, "Dynamic Supply Noise Measurement Circuit Composed of Standard Cells Suitable for In-Site Soc Power Integrity Verification," In Proc. IEEE/ACM Asia and South Pacific Design Automation Conference, pages 107-108, January 2008.

[67] R. Hashimoto, K. Kato, G. Fujta, and T. Onoye, "VLSI Architecture of H.264 RDO-BASED Block Size Decision for 1080 HD," In Proc. PCS, November 2007.

[68] R. Hashimoto, T. Matsumura, Y. Nozato, K. Watanabe, and T. Onoye, "Implementation of Object Attention Based on Multi-Agent Attractor Selection," In Proc. SISB, November 2007.

[69] K. Takahashi, Y. Nozato, H. Okuhata, and T. Onoye, "VLSI Architecture for Real-Time Retinex Video Image Enhancement," In Proc. Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI 2007), pages 81--86, October 2007.

[70] K.Hamamoto, H.Fuketa, M.Hashimoto, Y.Mitsuyama, and T.Onoye, "A Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability," In Proc. Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI 2007), pages 233-237, October 2007.

[71] Y. Ogasahara, M. Hashimoto, and T. Onoye, "Dynamic Supply Noise Measurement with All Digital Gated Oscillator for Evaluating Decoupling Capacitance Effect," In Proc. IEEE Custom Integrated Circuits Conference, pages 783-786, September 2007.

[72] Mohd Nadzrul Bin Mohd Nor, T. Matsumura, and T. Onoye, "Direction of Arrival Estimation Improvement of Speech on a Two-Microphone Array," In IASTED International Conference on Signal and Image Processing, pages 576-115, August 2007.

[73] K. Shinkai, M. Hashimoto, and T. Onoye, "Future Prediction of Self-Heating in Short Intra-Block Wires," In Proc. International Symposium on Quality Electronic Design (ISQED), pages 660-665, March 2007.

[74] K. Watanabe, M. Ise, T. Onoye, H. Niwamoto, and I. Keshi, "An Energy-Efficient Architecture of Wireless Home Network Based on Mac Broadcast and Transmission Power Control," In International Conference on Consumer Electronics Digest of Technical Papers, P1-20, January 2007.

[75] R. Hashimoto, K. Kato, G. Fujta, and T. Onoye, "VLSI Architecture of H.264 Block Size Decision Based on Rate-Distortion Optimization," In Proc. ISPACS, pages 618--621, December 2006.

[76] K. Shinkai, M. Hashimoto, A. Kurokawa, and T. Onoye, "A Gate Delay Model Focusing on Current Fluctuation Over Wide-Range of Process and Environmental Variability," In Proc. International Conference on Computer-Aided Design (ICCAD), pages 47-53, November 2006.

[77] Y. Ogasahara, M. Hashimoto, and T. Onoye, "Quantitative Prediction of On-Chip Capacitive and Inductive Crosstalk Noise and Discussion on Wire Cross-Sectional Area Toward Inductive Crosstalk Free Interconnects," Proc. IEEE International Conference on Computer Design, pages 70--75, October 2006.

[78] J. Ashida, R. Miyamoto, H. Tsutsui, T. Onoye, and Y. Nakamura, "Probabilistic Pedestrian Tracking Based on a Skeleton Model," In Proc. International Conference on Image Processing, pages 2825--2828, October 2006.

[79] Y. Ogasahara, M. Hashimoto, and T. Onoye, "Measurement of Inductive Coupling Effect on Timing in 90nm Global Interconnects," In Proc. IEEE Custom Integrated Circuits Conference, pages 721--724, September 2006.

[80] Y. Ogasahara, T. Enami, M. Hashimoto, T. Sato, and T. Onoye, "Measurement Results of Delay Degradation Due to Power Supply Noise Well Correlated with Full-Chip Simulation," In Proc.~IEEE Custom Integrated Circuits Conference, pages 861--864, September 2006.

[81] A. Kosaka and T. Onoye, "Pipeline Processing of Continuous Speech Recognition Algorithm for Embedded System Implementation," In Proc. International Technical Conference on Circuits/Systems, Computers and Communication, volume Ⅱ, pages 373--376, July 2006.

[82] F. Hyuga, T. Masuzaki, H. Tsutsui, T. Onoye, and Y. Nakamura, "A JPEG Coding Scheme for High Fidelity Images by Halftoning Less Signification Extra Bits," In Proc. International Technical Conference on Circuits/Systems, Computers and Communication, volume Ⅲ, pages 97--100, July 2006.

[83] K. Tsujino, W. Kobayashi, T. Onoye, and Y. Nakamura, "Automated Design of Digital Filters for 3-D Sound Localization in Embedded Applications," In Proc. International Conf. Audio, Speech, and Signal Processing (ICASSP2006), V.349--V.352, May 2006.

[84] H. Sugano, H. Tsutsui, T. Masuzaki, T. Onoye, H. Ochi, and Y. Nakamura, "Efficient Memory Architecture for JPEG2000 Entropy Codec," In Proc. International Symposium on Circuits and Systems, pages 2881--2884, May 2006.

[85] Y. Mitsuyama, R. Imai, K. Takahashi, T. Onoye, and I. Shirakawa, "Domain-Specific Reconfigurable Architecture for Media Processing," In Proc. Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI 2006), pages 322--327, April 2006.

[86] A. Kotani, Y. Tanemura, Y. Mitsuyama, Y. Asai, Y. Nakamura, and T. Onoye, "Contour-Based Gravity Center Evaluation of Characters," In Proc. EUROMEDIA, pages 15--20, April 2006.

[87] K. Shinkai, M. Hashimoto, A. Kurokawa, and T. Onoye, "A Gate Delay Model Focusing on Current Fluctuation Over Wide-Range of Process and Environmental Variability," In Proc. International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pages 59-64, February 2006.

[88] Z. Guo, Y. Nishikawa, R. Y. Omaki, T. Onoye, and I. Shirakawa, "A Low-Complexity FEC Assignment Scheme for Motion JPEG2000 Over Wireless Network," In International Conference on Consumer Electronics(ICCE2006), digest of technical papers, Las Vegas, Nevada, USA, pages 391--392, January 2006.

[89] Y. Ogasahara, M. Hashimoto, and T. Onoye, "Measurement and Analysis of Delay Variation Due to Inductive Coupling," In Proc. IEEE Custom Integrated Circuits Conference, pages 305--308, September 2005.

[90] Huynh Van Nhat, T. Imanaka, G. Fujita, T. Onoye, and I. Shirakawa, "Real-Time Human Object Extraction for Mobile Terminal," In in Proc.The 20th Commemorative International Technical Conference on Circuits/Systems, Computers and Communications(ITC-CSCC2005), Jeju, Korea, volume 3, pages 1015-1016, July 2005.

[91] Y. Mitsuyama, R. Imai, K. Takahashi, T. Onoye, and I. Shirakawa, "An Approach for Area-Efficient Coarse-Grained Reconfigurable Architecture Dedicated to Media Processing," In Proc. International Technical Conference of Circuits/Systems, Computers and Communications (ITC-CSCC2005), pages 131--132, July 2005.

[92] T. Matsumura, N. Iwanaga, T. Onoye, W. Kobayashi, I. Shirakawa, and I. Arungsrisangchai, "3D Sound Movement System for Embedded Applications," In in Proc. IEEE International Symposium on Circuits and Systems (ISCAS2005), Kobe, Japan, pages 5345-5348, May 2005.

[93] R. Miyamoto, H. Sugita, Y. Hayashi, H. Tsutsui, T. Masuzaki, T. Onoye, and Y. Nakamura, "High Quality Motion JPEG2000 Coding Scheme Based on the Human Visual System," In Proc. IEEE Int’l Symp. Circuits and Systems, pages 2096--2099, May 2005.

[94] T. Matsumura, N. Iwanaga, W. Kobayashi, T. Onoye, and I. Shirakawa, "Embedded 3D Sound Movement System Based on Feature Extraction of Head-Related Transfer Function," In in Proc.~International Conference on Consumer Electronics (ICCE2005), digest of technical papers, Las Vegas, Nevada, USA, 7.1-2, January 2005.

[95] R. Miyamoto, Y. Hayashi, H. Tsutsui, T. Masuzaki, T. Onoye, and Y. Nakamura, "Video Quality Enhancement for Motion JPEG2000 Encoding Based on the Human Visual System," In Proc. IEEE Asia Pacific Conference on Circuits and Systems, pages 1161--1164, December 2004.

[96] N. Iwanaga, W. Kobayashi, K. Furuya, T. Onoye, and I. Shirakawa, "VLSI Implementation of 3D Sound Image Movement for Embedded Systems," In in Proc. IEEE Region 10 Conference (TENCON) 2004, A--021, November 2004.

[97] K. Tsujino, W. Kobayashi, T. Izumi, T. Onoye, and Y. Nakamura, "Realtime Filter Redesign for Interactive 3-D Sound Systems," In Proc. IEEE Region 10 Conference, pages 124--127, November 2004.

[98] N. Iwanaga, W. Kobayashi, K. Furuya, T. Onoye, and I. Shirakawa, "VLSI Implementation of a 3D Sound Movement System," In in Proc. The 12th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI) 2004, pages 121-125, October 2004.

[99] Y. Mitsuyama, M. Kimura, T. Onoye, and I. Shirakawa, "Embedded Architecture of IEEE802.11i Cipher Algorithms," In in Proc. 2004 IEEE International Symposium on Consumer Electronics (ISCE2004), pages 241--246, September 2004.

[100] S. Maeta, A. Kosaka, A. Yamada, T. Onoye, T. Chiba, and I. Shirakawa, "C-Based Hardware Design of IMDCT Accelerator for Ogg Vorbis Decoder," In in Proc.12th European Signal Processing Conference (EUSIPCO 2004), pages 1361--1364, September 2004.

[101] H. Tsutsui, T. Masuzaki, Y. Hayashi, Y. Taki, T. Izumi, T. Onoye, and Y. Nakamura, "Scalable Design Framework for JPEG2000 System Architecture," In Proc. Asia-Pacific Computer Systems Architecture Conference, pages 6--11, September 2004.

[102] J. Ashida, R. Miyamoto, H. Tsutsui, T. Onoye, and Y. Nakamura, "A Scalable Approach for Estimation of Focus of Expansion," In Proc. IASTED International Conference on Visualization, Imaging, and Image Processing, pages 6--11, September 2004.

[103] Y. Ogasahara, M. Ise, T. Onoye, and I. Shirakawa, "Architecture of Turbo Decoder for W-CDMA by Configurable Processor," In Proc.The 2004 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2004), Sendai, Japan, F2P-27-1--7F2P-27-4, page 7, July 2004.

[104] T. Onoye, H. Tsutsui, G. Fujita, Y. Nakamura, and I. Shirakawa, "Embedded System Implementation of Scalable and Object-Based Video Coding," In in Proc. of World Automation Congress (WAC) , International Forum on Multimedia and Image Processing (IFMIP), IFMIP076, June 2004.

[105] H. Sugita, Q.-M. Vu, T. Masuzaki, H. Tsutsui, T. Izumi, T. Onoye, and Y. Nakamura, "JPEG2000 High-Speed Progressive Decoding Scheme," In Proc. IEEE International Symposium on Circuits and Systems, pages 873--876, May 2004.

[106] A. Kosaka, S. Yamaguchi, H. Okuhata, T. Onoye, and I. Shirakawa, "SoC Design of Ogg Vorbis Decoder Using Embedded Processor," In in Proc. 2004 Computing Frontier Conference, pages 481--487, April 2004.

[107] K. Tsujino, A. Shigiya, W. Kobayashi, T. Izumi, T. Onoye, and Y. Nakamura, "An Implementation of Moving 3-D Sound Synthesis System Based on Floating Point Dsp," In Proc. IEEE International Symposium on Signal Processing and Information Technology, WA4-8.1-WA4-8.4, December 2003.

[108] K. Tsujino, A. Shigiya, T. Izumi, T. Onoye, Y. Nakamura, and W. Kobayashi, "A Dsp-Based 3-D Sound Synthesis System for Moving Sound Images," In Proc. GAME-ON Conference, pages 23--25, November 2003.

[109] K. Hontani, T. Imanaka, G. Fujita, T. Onoye, and I. Shirakawa, "Modified Snake: Real-Time Face Object Extraction for Video Phone," In in Proc. IEEE International Conference on Image Processing(ICIP2003), Barcelona, Spain, volume III, pages 873--876, September 2003.

[110] M. Ise, Y. Ogasahara, T. Onoye, and I. Shirakawa, "Implementation of W-CDMA Channel Codec by Configurable Processors," In Proc. Sixth Baiona Workshop on Signal Processing in Communications, pages 205--210, September 2003.

[111] H.-S. Song, H. Okada, G. Fujita, T. Onoye, and I. Shirakawa, "Efficient Error Recovery Scheme for MPEG-4 Video Coding," In in Proc. The 2003 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2003), Kang-Woo Do, Korea, volume 2, pages 1328--1331, July 2003.

[112] A. Kotani, Y. Asai, Y. Nakamura, S. Okada, N. Koyama, K. Yamane, Y.Okano, Y. Mitsuyama, and T. Onoye, "Visibility Font Technology on High Resolution Color LCD "LCFONT.C"," In in Proc. The 2003 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2003), Kang-Woo Do, Korea, volume 1, pages 535--538, July 2003.

[113] S. Yamaguchi, A. Kosaka, H. Okuhata, T. Onoye, and I. Shirakawa, "Low Power Ogg Vorbis Decoder by Embedded Processor," In in Proc. The 2003 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2003), Kang-Woo Do, Korea, volume 1, pages 565--568, July 2003.

[114] T. Matsumura, N. Iwanaga, W. Kobayashi, T. Onoye, and I. Shirakawa, "Feature Extraction of Head-Related Transfer Function for 3D Sound Movement," In in Proc. The 2003 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2003), Kang-Woo Do, Korea, volume 1, pages 685--688, July 2003.

[115] N. Iwanaga, W. Kobayashi, K. Furuya, T. Onoye, and I. Shirakawa, "Embedded Implementation of Acoustic Field Enhancement for Stereo Sound Sources," In in IEEE 29th International Conference on Consumer Electronics (ICCE2003), digest of technical papers, Los Angeles, Carifornia, USA, pages 256--257, June 2003.

[116] T. Okada, T. Uchida, T. Onoye, and I. Shirakawa, "A Novel Signal Processing Scheme for Next Generation GNSS Receiver," In in Proc. the 8th ISU International Symposium, Strasbourg, France, May 2003.

[117] S. Komata, A. Pal, N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa, "Interactive Interface of Realtime 3D Sound Movement for Embedded Applications," In in Proc. IEEE International Symposium on Circuits and Systems (ISCAS2003) , Bankok, Thailand, volume II, pages 520--523, May 2003.

[118] Y. Hayashi, H. Tsutsui, T. Masuzaki, T. Izumi, T. Onoye, and Y. Nakamura, "Design Framework for JPEG2000 Encoding System Architecture," In Proc. International Symposium on Circuits and Systems, pages 740--743, May 2003.

[119] T. Okada, T. Uchida, T. Onoye, and I. Shirakawa, "A Novel Signal Processing Scheme for Next Generation GNSS Receiver and Its VLSI Implementation," In in Proc. International Signal Processing Conference , Dallas, number 357, April 2003.

[120] N. Iwanaga, W. Kobayashi, K. Furuya, N. Sakamoto, T. Onoye, and I.Shirakawa, "Low Cost Approach to Acoustic Field Enhancement for Stereo Headphones," In in Proc. Euromedia 2003, Plymouth, United Kingdom, pages 32--36, April 2003.

[121] T. Yuasa, A. Tomita, T. Izumi, T. Onoye, and Y. Nakamura, "An Approach for Circuit Size Reduction by Variable Reordering for Pca-Chip2," In Proc. Workshop on Synthesis and System Integration of Mixed Information Technologies, pages 217--221, April 2003.

[122] T. Nakagawa, G. Fujita, T. Onoye, and I. Shirakawa, "Vlsi Architecture for Mpeg-4 Core Profile Codec Core," In Proc. Workshop on Synthesis and System Integration of Mixed Information Technologies, pages 365--371, April 2003.

[123] Y. Hayashi, H. Tsutsui, T. Masuzaki, T. Izumi, T. Onoye, and Y. Nakamura, "Scalable Design Framework for JPEG2000 Encoder Architecture," In Proc. Workshop on Synthesis and System Integration of Mixed Information Technologies, pages 372--376, April 2003.

[124] T. Yuasa, Y. Soga, T. Izumi, T. Onoye, and Y. Nakamura, "An Improved Communication Channel in Dynamic Reconfigurable Device for Multimedia Applications," In Proc. EUROMEDIA, pages 152--157, April 2003.

[125] K. Hontani, T. Imanaka, G. Fujita, T. Onoye, and I. Shirakawa, "Realtime Face Object Extraction Algorithm for Video Phone," In in Proc. IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2002), Orchard Road, Singapore, volume 1, pages 35--38, December 2002.

[126] Y. Ohtani, H. Nakaoka, T. Tomaru, K. Maruyama, T. Chiba, T. Onoye, and I. Shirakawa, "Implementation of Wireless MPEG2 Transmission System Using IEEE 802.11b PHY," In ibid, volume 1, pages 39--44, December 2002.

[127] N. Iwanaga, W. Kobayashi, K. Furuya, N. Sakamoto, T. Onoye, and I. Shirakawa, "Embedded Implementation of Acousitic Field Enhancement for Stereo Headphones," In ibid, volume 1, pages 51--54, December 2002.

[128] A. Kosaka, S. Yamaguchi, H. Okuhata, T. Onoye, and I. Shirakawa, "VLSI Implementation of Ogg Vorbis Decoder for Embedded Applications," In in Proc. 15th Annual IEEE International ASIC/SoC Conference(ASIC/SoC2002), Rochester, N.Y., pages 20--24, September 2002.

[129] A. Kosaka, S. Yamaguchi, H. Okuhata, T. Onoye, and I. Shirakawa, "A Hardware Implementation of Ogg Vorbis Audio Decoder with Embedded Processor," In in Proc. 17th Annual International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2002), Phuket, Thailand, pages 94--97, July 2002.

[130] S. Komata, N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa, "Synthesis of 3D Sound Movement by Embedded DSP," In ibid, pages 117--120, July 2002.

[131] H. Okada, A.-E. Shiitev, H.-S. Song, G. Fujita, T. Onoye, and I. Shirakawa, "Digital Watermark Based Error Detection for MPEG-4 Bitstream Error," In ibid, pages 152--155, July 2002.

[132] T. Kaya, R. Miyamoto, T. Onoye, and I. Shirakawa, "Embedded System for Video Coding with Logic-Enhanced DRAM and Configurable Processor," In ibid, pages 216--219, July 2002.

[133] H.-S. Song, H. Okada, G. Fujita, T. Onoye, and I. Shirakawa, "Hybrid Error Concealment Algorithm for MPEG-4 Videodecoders," In ibid, pages 611--614, July 2002.

[134] W. Kobayashi, K. Furuya, N. Sakamoto, T. Onoye, and I. Shirakawa, "`Out-Of-Head' Acoustic Field Enhancement for Stereo Headphones by Embedded DSP," In in IEEE 28th International Conference on Consumer Electronics (ICCE2002), digest of technical papers, Cardiff, Wales, pages 222--223, June 2002.

[135] Y. Ohtani, N. Kawahara, T. Onoye, I. Shirakawa, and T. Chiba, "MAC LSI Design for Wireless MPEG2 Transmission Over IEEE802.11b PHY," In ibid, pages 242--243, June 2002.

[136] Y. Mitsuyama, Z. Andales, T. Onoye, and I. Shirakawa, "Burst Mode: a New Acceleration Mode for 128-Bit Block Ciphers," In in Proc. IEEE 24th Custom Integrated Circuits Conference (CICC2002), Orland, Florida, pages 151--154, May 2002.

[137] Y. Uchida, M. Ise, T. Onoye, I. Shirakawa, and I. Arungsrisangchai, "VLSI Architecture of Digital Matched Filter and Prime Interleaver for W-CDMA," In Proc. IEEE International Symposium on Circuits and Systems (ISCAS2002), Phoenix, Arizona, volume III, pages 269--272, May 2002.

[138] Y. Mitsuyama, Z. Andales, T. Onoye, I. Shirakawa, and I. Arungsrisangchai, "VLSI Architecture of Burst Mode Acceleration for 128-Bit Block Ciphers," In ibid, volume II, pages 344--347, May 2002.

[139] H. Mizuno, H. Kobayashi, T. Onoye, and I. Shirakawa, "Power Estimation at Architecture Level for Embedded Systems," In ibid, volume II, pages 476--479, May 2002.

[140] Y. Ohtani, N. Kawahara, T. Tomaru, K. Maruyama, T. Onoye, I. Shirakawa, and T. Chiba, "Error Correction Block Based ARQ Protocol for Wireless Digital Video Transmission," In ibid, volume I, pages 605--608, May 2002.

[141] M. Kimura, M. H. Miki, T. Onoye, and I. Shirakawa, "A Java Accelerator for High Performance Embedded Systems," In in Proc. 4th International Conference of Massively Parallel Computing Systems (MPCS 2002), Ischia, Italy, 2, April 2002.

[142] N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa, "DSP Implementation of Realtime 3D Sound Synthesis Algorithm for Monaural Sound Source," In in Proc. EUROMEDIA 2002, Modena, Italy, pages 123--127, April 2002.

[143] M. H. Miki, M. Kimura, T. Onoye, and I. Shirakawa, "High Performance Java Hardware Engine and Software Kernel for Embedded Systems," In in Proc. 11th IFIP International Conference on Very Large Scale Integration (VLSI-SOC 2001), Montpellier-Le Corum, France, pages 365--369, December 2001.

[144] H. Mizuno, H. Kobayashi, T. Onoye, and I. Shirakawa, "An Architecture Level Power Estimation Method for Embedded Systems," In in Proc. Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI 2001), Nara, Japan, pages 78--85, October 2001.

[145] Z. Andales, Y. Mitsuyama, T. Onoye, and I. Shirakawa, "System Performance Evaluation of High-Speed Burst Mode for 128-Bit Block Ciphers," In in Proc. Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI 2001), Nara, Japan, pages 332--339, October 2001.

[146] M. Kimura, M. H. Miki, T. Onoye, and I. Shirakawa, "High Performance Java Execution for Embedded Systems," In in Proc. Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI 2001), Nara, Japan, pages 346--350, October 2001.

[147] M. Ise, Y. Uchida, T. Onoye, and I. Shirakawa, "System-On-A-Chip Architecture for W-CDMA Baseband Modem LSI," In in Proc. The 4th International Conference on ASIC (ASICON 2001), Shanghai, pages 364--369, October 2001.

[148] M. Furuie, T. Onoye, S. Tsukiyama, and I. Shirakawa, "Two-Dimensional Array Layout for NMOS 4-Phase Dynamic Logic," In in Proc. The 8th IEEE International Conference on Electronics, Circuits and Systems(ICECS 2001), Malta, pages 589--592, September 2001.

[149] N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa, "DSP Implementaion of 3D Sound Localization Algorithm for Monaural Sound Source," In in Proc. The 8th IEEE International Conference on Electronics, Circuits and Systems(ICECS 2001), Malta, pages 1061--1064, September 2001.

[150] N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa, "DSP Implementation of Low Computational 3D Sound Localization Algorithm," In in Proc. 200l IEEE Workshop on Signal Processing Systems, Design and Implementation(SIPS 2001), Antwerp, Belgium, pages 109--116, September 2001.

[151] Y. Mitsuyama, Z. Andales, T. Onoye, and I. Shirakawa, "VLSI Implementation of High Performance Burst Mode for 128-Bit Block Ciphers," In in Proc. 14th Annual IEEE International ASIC/SoC Conference (ASIC/SoC2001), Washington, D.C., pp. W.1.1.1--W.1.1.5, September 2001.

[152] H. Okada, H. S. Song, G. Fujita, T. Onoye, and I. Shirakawa, "Error Detection Based on Check Marker Embedding for MPEG-4 Video Coding," In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC '01), Tokushima, Japan, pages 96--99, July 2001.

[153] H. S. Song, H. Okada, G. Fujita, T. Onoye, and I. Shirakawa, "Error Concealment Algorithm by Motion Estimation Method for MPEG-4 Video Decoder," In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC '01), Tokushima, Japan, pages 104--107, July 2001.

[154] T. Song, G. Fujita, T. Onoye, and I. Shirakawa, "Low Power Architecture for H.263 Version2 Codec," In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC '01), Tokushima, Japan, pages 620--623, July 2001.

[155] N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa, "DSP Implementation of Realtime 3D Sound Localization Algorithm," In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC '01), Tokushima, Japan, pages 1140--1143, July 2001.

[156] N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa, "Low Power DSP Implementation of 3D Sound Localization for Monaural Sound Source," In in Proc. World Multiconference on Systemics, Cybernetics and Informatics (SCI 2001), Orlando, Florida, USA, pages 173--177, July 2001.

[157] Y. Mitsuyama, Z. Andales, T. Onoye, and I. Shirakawa, "VLSI Architecture of Dynamically Reconfigurable Hardware-Based Cipher," In in Proc. IEEE International Symposium on Circuits and Systems (ISCAS2001) , Sydney, Australia, volume IV, pages 734--737, May 2001.

[158] Z. Andales, Y. Mitsuyama, T. Onoye, and I. Shirakawa, "A High Performance Burst Mode Approach for 128-Bit Block Ciphers," In in Proc. EUROMEDIA2001, Valencia, Spain, pages 146--150, April 2001.

[159] Y. Mitsuyama, Z. Andales, T. Onoye, and I. Shirakawa, "A Dynamically Reconfigurable Hardware-Based Cipher Chip," In in Proc. Asia and South Pacific Design Automation Conference (ASP-DAC 2001), Yokohama, Japan, pages 11--12, January 2001.

[160] R. Y. Omaki, Y. Dong, M. H. Miki, M. Furuie, D. Taki, M. Tarui, G. Fujita, T. Onoye, and I. Shirakawa, "Realtime Wavelet Video Coder Based on Reduced Memory Accessing," In in Proc.~Asia and South Pacific Design Automation Conference (ASP-DAC 2001), Yokohama, Japan, pages 15--16, January 2001.

[161] S. Hashimoto, A. Niwa, H. Okuhata, T. Onoye, and I. Shirakawa, "VLSI Implementation of Portable MPEG-4 Audio Decoder," In in Proc. International ASIC/SOC Conference (ASIC/SOC 2000), Arington, VA, USA, pages 80--84, September 2000.

[162] Y. Dong, R. Y. Omaki, T. Onoye, and I. Shirakawa, "VLSI Implementation of a Reduced Memory Bandwidth Realtime EZW Video Coder," In in Proc. International Conference on Image Processing (ICIP 2000), volume III, pages 126--129, September 2000.

[163] N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa, "Low Power DSP Implementation of 3D Sound Localization," In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2000), Pusan, Korea, pages 253--256, July 2000.

[164] W. Kobayashi, N. Sakamoto, T. Onoye, and I. Shirakawa, "3D Acoustic Image Localization Algorithm by Embedded DSP," In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2000), Pusan, Korea, pages 264--267, July 2000.

[165] R. Kuroda, G. Fujita, T. Onoye, and I. Shirakawa, "Discrete Cosine Transformer with Variable-Length Basis Vector for MPEG-4 Video Codec," In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2000), Pusan, Korea, pages 811--814, July 2000.

[166] Y. Mitsuyama, Z. Andales, T. Onoye, and I. Shirakawa, "VLSI Implementation of Dynamically Reconfigurable Hardware-Based Cryptosystem," In in Symposium on VLSI Circuits Digest of Technical Papers, Hawaii, USA, pages 204--205, June 2000.

[167] Z. Andales, Y. Mitsuyama, T. Onoye, and I. Shirakawa, "Chameleon: a Dynamically Reconfigurable Hardware-Based Cryptosystem," In in Proc. EUROMEDIA2000 , Antwerp, Belgium, pages 90--94, May 2000.

[168] R. Y. Omaki, Y. Dong, M. H. Miki, M. Furuie, S. Yamada, D. Taki, M. Tarui, G. Fujita, T. Onoye, and I. Shirakawa, "VLSI Implementation of a Realtime Wavelet Video Coder," In in Proc. Custom Integrated Circuits Conference (CICC 2000), Florida, USA, pages 543--546, May 2000.

[169] M. Furuie, B. Y. Song, Y. Yoshida, T. Onoye, and I. Shirakawa, "Layout Generation of Array Cell for NMOS 4-Phase Dynamil Logic," In in Proc. ASP-DAC2000, pages 529--532, January 2000.

[170] R. Y. Omaki, G. Fujita, T. Onoye, and I. Shirakawa, "Video Coding Algorithm Based on Modified Discrete Wavelet Transform," In in Proc. NOLTA'99, volume I, pages 251--254, November 1999.

[171] R. Y. Omaki, G. Fujita, T. Onoye, and I. Shirakawa, "Architecture of Embedded Zerotree Wavelet Based Real-Time Video Coder," In in Proc. 12th IEEE ASIC/SOC Conference, pages 137-141, October 1999.

[172] R. Y. Omaki, G. Fujita, T. Onoye, and I. Shirakawa, "Embedded Zerotree Wavelet Based Algorithm for Video Compression," In in Proc. IEEE Region 10 Conference (TENCON '99), pp.II-1343--1346, September 1999.

[173] M. Furuie, B. Y. Song, Y. Yoshida, T. Onoye, and I. Shirakawa, "Layout Generation for Low-Power NMOS 4-Phase Dynamic Logic Array," In in Proc. IEEE Region 10 Conference (TENCON '99), pages 872--875, September 1999.

[174] M. Tarui, M. Oshita, T. Onoye, and I. Shirakawa, "High-Speed Implementation of JBIG Arithmetic Coder," In in Proc. IEEE Region 10 Conference (TENCON '99), pages 1291--1294, September 1999.

[175] B. Y. Song, M. Furuie, Y. Yoshida, T. Onoye, and I. Shirakawa, "Array Macro Cell Architecture for Low-Power NMOS 4-Phase Dynamic Logic," In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC '99), Sado, Japan, pages 561--564, July 1999.

[176] M. Oshita, M. Tarui, T. Onoye, and I. Shirakawa, "Pipelined Implementation of JBIG Arithmetic Coder," In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC '99), Sado, Japan, pages 470--473, July 1999.

[177] M. H. Miki, D. Taki, G. Fujita, T. Onoye, I. Shirakawa, T. Fujiwara, and T. Kasami, "Recursive Maximum Likelihood Decoder for High-Speed Satellite Communication," In in Proc. IEEE International Symposium on Circuits and Systems (ISCAS '99) , Orland, USA, volume IV, pages 572--575, June 1999.

[178] H. Fujishima, Y. Takemoto, T. Yoneda, T. Onoye, and I. Shirakawa, "Hybrid Media-Processor Core for Natural and Synthetic Video Decoding," In in Proc. IEEE International Symposium on Circuits and Systems (ISCAS '99) , Orland, USA, volume IV, pages 275--278, June 1999.

[179] G. Fujita, H. Okuhata, M. H. Miki, T. Onoye, and I. Shirakawa, "Low-Power Architecture of H.324 Codec Dedicated to Mobile Computing," In in Proc. EUROMEDIA'99 , Munich, Germany, pages 145--149, April 1999.

[180] K. Asari, Y. Mitsuyama, T. Onoye, I. Shirakawa, H. Hirano, T. Honda, T. Otsuki, T. Baba, and T. Meng, "Multi-Mode and Multi-Level Technologies for FeRAM Embedded Reconfigurable Hardware," In in Proc. IEEE Internatinal Solid-State Circuits Conference, pages 106--107, February 1999.

[181] H. Fujisima, Y. Takemoto, T. Yoneda, T. Onoye, and I. Shirakawa, "Hybrid VLSI Architecture for Motion Compensation and Texture Mapping," In in Proc. IEEE International Workshop on Intelligent Signal Processing and Communication Systems, pages 383--386, November 1998.

[182] J. Fan, G. Fujita, M. Furuie, T. Onoye, and I. Shirakawa, "Structual Objeco-Oriented Video Segmentation and Representation Algorithm," In in Proc. IEEE International Workshop on Intelligent Signal Processing and Communication Systems, pages 78--82, November 1998.

[183] H. Fujisima, Y. Takemoto, T. Onoye, I. Shirakawa, and K. Matsumura, "Matrix-Vector Multiplier Module for Natural/Synthetic Hybrid Video Coding," In in Proc. IEEE Asia Pacific Conference on Circuits and Systems, pages 631--634, November 1998.

[184] B.Y. Song, Y. Yoshida, T. Onoye, and I. Shirakawa, "Low-Power Implementation by a New Logic Scheme of NMOS 4-Phase Dynamic Logic," In in Proc. Workshop on Synthesis and System Integration of Mixed Technologies, pages 235--240, October 1998.

[185] B.Y. Song, Y. Yoshida, T. Onoye, and I. Shirakawa, "Delay and Power Simulation for a New Logic Scheme of NMOS 4-Phase Dynamic Logic," In in Proc. European Simulation Symposium, pages 339--343, October 1998.

[186] J. Fan, G. Fujita, J. Yu, K. Miyanohana, T. Onoye, N. Ishiura, L. Wu, and I. Shirakawa, "Hierarchical Object-Oriented Image and Video Segmentation Algorithm Based on 2D Entropic Thresholding," In in Proc. Electronic Imaging and Multimedia Systems II, SPIE, pages 141--151, September 1998.

[187] Y. Takemoto, T. Yoneda, H. Fujishima, T. Onoye, and I. Shirakawa, "VLSI Implementation of Function Module for Texture Mapping and Motion Compensation," In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications, pages 179--182, July 1998.

[188] R. Y. Omaki, G. Fujita, T. Onoye, and I. Shirakawa, "Implementation of DWT and EZW Cores for a Bitrate Scalable Video Coder," In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications, pages 221--224, July 1998.

[189] H. Fujisima, Y. Takemoto, T. Onoye, and I. Shirakawa, "Matrix-Vector Multiplier for Natural/Synthetic Hybrid Video Coding," In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications, pages 1269--1272, July 1998.

[190] D. Taki, G. Fujita, T. Onoye, I. Shirakawa, T. Fujiwara, and T. Kasami, "VLSI Implementation of a Recursive Maximum Likelihood Decoder for High-Speed Satellite Communication," In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications, pages 1383--1386, July 1998.

[191] G. Fujita, H. Okuhata, M. H. Miki, T. Onoye, and I. Shirakawa, "Implementation of H.324 Audiovisual Codec for Mobile Computing," In in Proc. IEEE Custom Integrated Circuits Conference, pages 193--196, May 1998.

[192] H. Okuhata, M. H. Miki, T. Onoye, and I. Shirakawa, "A Low Power DSP Core Architecture for Low Bitrate Speech Codec," In in Proc. IEEE Int'l Conf. Acoustics, Sounds, and Signal Processing, pages 3121--3124, May 1998.

[193] T. Onoye, G. Fujita, H. Okuhata, M. H. Miki, and I. Shirakawa, "Low-Power Implementation of H.324 Audiovisual Codec Dedicated to Mobile Computing," In in Proc. Aia and South Pacific Design Automation Conference (ASP-DAC '98), pages 589-594, February 1998.

[194] T. Masaki, Y. Nakatani, T. Onoye, and K. Murakami, "Performance Evaluation of Shared VCI Cell for Multimedia ATM Network," In in Proc. International Seminar on Teletraffic and Network, pages 482-485, November 1997.

[195] H. Fujishima, Y. Takemoto, T. Onoye, I. Shirakawa, and S. Sakaguchi, "A Unified Media-Processor Architecure for Video Coding and Computer Graphics," In in Proc. International Workshop on Synthetic-Natural Hybrid Coding and Three Dimensional Imaging, pages 253-256, September 1997.

[196] M. H. Miki, G.Fujita, T. Onoye, and I. Sirakawa, "Low-Power H.263 Video CoDec Dedicated to Mobile Computing," In in Proc. International Symposium on Low Power Electronics and Design, pages 80-83, August 1997.

[197] Y. Yoshida, B. Y. Song, H. Okuhata, T. Onoye, and I. Shirakawa, "An Object Code Compression Approach to Embedded Processors," In in Proc. International Symposium on Low Power Electronics and Design, pages 265-268, August 1997.

[198] T. Masaki, Y. Nakatani, T. Onoye, and K. Murakami, "Fellow Cell Switching for Voice Communication on Multimedia ATM Network and Its VLSI Implementation," In in Proc. Int'l Technical Conference on Circuit/Systems, Computers and Communications, pages 1219-1222, July 1997.

[199] H. Fujisima, Y. Takemoto, T. Onoye, and I. Shirakawa, "Media-Processor Architecture Unified for Video Coding and 3D Graphics," In in Proc. Int'l Technical Conference on Circuit/Systems, Computers and Communications, pages 1223-1226, July 1997.

[200] G. Fujita, T. Onoye, and I. Sirakawa, "A New Motion Estimation Core Dedicated to H.263 VideoCoding," In in Proc. IEEE International Symposium on Circuits and Systems, pages 1161-1164, June 1997.

[201] T. Masaki, Y. Nakatani, T. Onoye, and K. Murakami, "Multimedia ATM Network Using Shared VCI Cell and VLSI Implementation of Rerouting Node," In in Proc. IEEE International Symposium on Circuits and Systems, pages 2793-2796, June 1997.

[202] K. Miyanohana, G. Fujita, K. Yanagida, T. Onoye, and I. Shirakawa, "VLSI Implementation of Single Chip Encoder/Decoder for Low Bitrate Visual Communication," In in Proc. IEEE Custom Integrated Circuits Conference, pages 229-232, May 1997.

[203] G. Fujita, T. Onoye, I. Shirakawa, S. Tsukiyama, and K. Matsumura, "Implementation of Half-Pel Precision Motion Estimator for MPEG2 MP@HL," In in Proc. IEEE Region 10 International Conference on Digital Signal Processing Applications (TENCON '96), pages 949-954, November 1996.

[204] K. Miyanohana, G. Fujita, T. Onoye, and I. Shirakawa, "VLSI Implementation of Edge Detector and Vector Quantizer for Very Low Bitrate Video Encoding," In in Proc. IEEE Asia Pacific Conference on Circuits and Systems (APCCAS '96), pages 480-483, November 1996.

[205] Y. Yoshida, B. Y. Song, H. Okuhata, T. Onoye, and I. Shirakawa, "Low-Power Consumption Architecture for Embedded Processor," In in Proc. 2nd International Conference on ASIC, pages 77-80, October 1996.

[206] K. Miyanohana, G. Fujita, T. Onoye, and I. Shirakawa, "Implementation of Very Low Bitrate Video Encoder Core," In in Proc. 2nd International Conference on ASIC, pages 131-134, October 1996.

[207] T. Onoye, G. Fujita, M. Takatsu, I. Shirakawa, and K. Matsumura, "A Single Chip Motion Estimator Dedicated to MPEG2 MP@HL," In in Proc. European Signal Processing Conference, pages 1479-1482, September 1996.

[208] G. Fujita, H. Okuhata, Y. Nakatani, T. Onoye, and I. Shirakawa, "Single Chip MPEG2 MP@ML Motion Estimator," In in Proc. Int'l Technical Conference on Circuits/Systems, Computers and Communications, pages 286-289, July 1996.

[209] K. Miyanohana, G. Fujita, T. Onoye, and I. Shirakawa, "VLSI Architecture for Very Low Bitrate Video Encoder Core," In in Proc. Int'l Technical Conference on Circuits/Systems, Computers and Communications, pages 294-297, July 1996.

[210] T. Onoye, G. Fujita, M. Takatsu, I. Shirakawa, K. Matsumura, H. Ariyoshi, and S. Tsukiyama, "VLSI Implementation of Hierarchical Motion Estimator for MPEG2 MP@HL," In in Proc. IEEE Custom Integrated Circuits Conference, pages 351-354, May 1996.

[211] T. Onoye, G. Fujita, M. Takatsu, I. Shirakawa, K. Matsumura, H. Ariyoshi, and S. Tsukiyama, "A VLSI Architecture of MPEG2 MP@HL Motion Estimator," In in Proc. IEEE Int'l Symposium on Circuits and Systems, pages 664-667, May 1996.

研究会等発表論文

[1] E. Aliwarga, J. Yu, M. Hatanaka, and T. Onoye, "Hardware Architecture of Generic Soft Cascaded Linear Svm Classifier," number 75, 電子情報通信学会ディペンダブルコンピューティング研究会, June 2015.

[2] S. Iizuka, Y. Higuchi, M. Hashimoto, and T. Onoye, "Area Efficient Device-Parameter Estimation Using Sensitivity-Configurable Ring Oscillator," 電子情報通信学会 VLSI設計技術研究会, March 2015.

[3] 亀田敏広, 郡浦宏明, 密山幸男, 橋本昌宜, 尾上孝雄, "スキャンパスを用いたＮＢＴＩ劣化抑制に関する研究," 情報処理学会DAシンポジウム, pages 201-206, 2011年8月.

[4] 郡浦宏明, 密山幸男, 橋本昌宜, 尾上孝雄, "NBTI による劣化予測におけるトランジスタ動作確率算出法の評価," 情報処理学会DAシンポジウム, pages 181-186, 2009年8月.

[5] 小笠原泰弘, 榎並孝司, 橋本昌宜, 佐藤高史, 尾上孝雄, "電源ノイズによる遅延変動の測定と電源ノイズを再現するフルチップシミュレーション手法," 信学技報, CPM2006-132, ICD2006-174, pages 19--23, 2007年1月.