論文誌

[1] S. Yano and N. Ishiura, "Embedded Memory Array Testing Using a Scannable Configuration," IEICE Trans. Fundamentals of Electronics,Communications and Computer Sciences, volume E80-A, number 10, pages 1934-1944, October 1997.

[2] S. Yano, K. Akagi, H. Inohara, and N. Ishiura, "Application of Full Scan Design to Embedded Memory Arrays," in Proc. IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, volume E80-A, number 3, March 1997.

国際会議

[1] Y. Konno, K. Nakamura, T. Bitoh, K. Saga, and S. Yano, "A Consistent Scan Design System for Large-Scale ASICs," In in Proc. Fifth Asian Test Symposium, pages 82-87, November 1996.

研究会等発表論文

[1] S. Yano, K. Akagi, and N. Ishiura, "A New Scan Path Approach to Memory Array Testing," In 電子情報通信学会第9回回路とシステム軽 井沢ワークショップ, pages 55-60, April 1996.