論文誌

[1] R. Harada, S. Abe, H. Fuketa, T. Uemura, M. Hashimoto, and Y. Watanabe, "Angular Dependency of Neutron Induced Multiple Cell Upsets in 65-Nm 10t Subthreshold Sram," IEEE Transactions on Nuclear Science, volume 59, number 6, pages 2791--2795, December 2012.

[2] T. Enami, S. Ninomiya, K. Shinkai, S. Abe, and M. Hashimoto, "Statistical Timing Analysis Considering Clock Jitter and Skew Due to Power Supply Noise and Process Variation," IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, volume 93-A, number 12, pages 2399-2408, December 2010.

[3] S. Abe, M. Hashimoto, and T. Onoye, "Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E91-A, number 12, pages 3481-3487, December 2008.

[4] K. Kawamoto, S. Mizuno, H. Abe, Y. Higuchi, H. Ishihara, H. Fukumoto, T. Watanabe, S. Fujino, and I. Shirakawa, "A Single Chip Automotive Control LSI Using SOI Bipolar Complimentary MOS Double-Diffused MOS," The Japan Society of Applied Physics, volume 40, number 4B, pages 2891--2896, April 2001.

国際会議

[1] S. Hirokawa, R. Harada, M. Hashimoto, K. Sakuta, and Y. Watanabe, "Neutron-Induced Seu and Mcu Rate Characterization and Analysis of Sotb and Bulk Srams at 0.3v Operation," IEEE Nuclear and Space Radiation Effects Conference (NSREC), July 2015.

[2] R. Harada, S. Abe, H. Fuketa, T. Uemura, M. Hashimoto, and Y. Watanabe, "Angular Dependency of Neutron Induced Multiple Cell Upsets in 65-Nm 10t Subthreshold Sram," IEEE Nuclear and Space Radiation Effects Conference, July 2012.

[3] S. Abe, K. Shinkai, M. Hashimoto, and T. Onoye, "Clock Skew Reduction by Self-Compensating Manufacturing Variability with On-Chip Sensors," In Proc. Great Lakes Symposium on VLSI (GLSVLSI), May 2010.

[4] T. Enami, S. Ninomiya, K. Shinkai, S. Abe, and M. Hashimoto, "Statistical Timing Analysis Considering Clock Jitter and Skew Due to Power Supply Noise and Process Variation," In Proc. International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), pages 41-46, March 2010.

[5] S. Abe, K. Shinkai, M. Hashimoto, and T. Onoye, "Clock Skew Reduction by Self-Compensating Manufacturing Variability with On-Chip Sensors," In Proc. International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), March 2010.

[6] S. Watanabe, M. Hashimoto, and T. Sato, "A Case for Exploiting Complex Arithmetic Circuits Towards Performance Yield Enhancement," In Proceedings of International Symposium on Quality Electronic Design (ISQED), pages 401--407, March 2009.

[7] S. Watanabe, M. Hashimoto, and T. Sato, "Cascading Dependent Operations for Mitigating Timing Variability," In Proceedings. of Workshop on Quality-Aware Design (W-QUAD), June 2008.

[8] S. Abe, M. Hashimoto, and T. Onoye, "Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution," In Proc. International Symposium on Quality Electronic Design (ISQED), pages 520-525, March 2008.

[9] K. Kawamoto, S. Mizuno, H. Abe, Y. Higuchi, S. Fujino, and I. Shirakawa, "A Shingle Chip Automotive Control LSI Using SOI BiCDMOS," In in Proc. of 2000 International Conference on Solid State Device and Materials, pages 486-487, August 2000.