論文誌

[1] M. Hashimoto, T. Ijichi, S. Takahashi, S. Tsukiyama, and I. Shirakawa, "Transistor Sizing of LCD Driver Circuit for Technology Migration," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E90-A, number 12, pages 2712--2717, December 2007.

[2] M. Ise, Y. Ogasahara, K. Watanabe, M. Hatanaka, T. Onoye, H. Niwamoto, I. Keshi, and I. Shirakawa, "Design and Implementation of Home Network Protocol for Appliance Control Based on IEEE 802.15.4," International Journal of Computer Science and Network Security, volume 7, number 7, pages 20-30, July 2007.

[3] S. Takahashi, S. Tsukiyama, M. Hashimoto, and I. Shirakawa, "A Sampling Switch Design Procedure for Active Matrix Liquid Crystal Displays," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E89-A, number 12, pages 3538--3545, December 2006.

[4] S. Takahashi, S. Tsukiyama, M. Hashimoto, and I. Shirakawa, "A Sampling Switch Design Procedure for Active Matrix Liquid Crystal Displays," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E89-A, number 12, pages 3538-3545, December 2006.

[5] G. Fujita, T. Imanaka, H. V. Nhat, T. Onoye, and I. Shirakawa, "Real-Time Human Object Extraction Method for Mobile Systems Based on Color Space Segmentation," In IEICE Trans. Fundamentals, volume E89-A, number 4, pages 941--949, April 2006.

[6] Z. Guo, Y. Nishikawa, R. Y. Omaki, T. Onoye, and I. Shirakawa, "A Low-Complexity FEC Assignment Scheme for Motion JPEG2000 Over Wireless Network," IEEE Transactions on Consumer Electronics, volume 52, number 1, pages 81--86, February 2006.

[7] M. Ise, Y. Ogasahara, T. Onoye, and I. Shirakawa, "W-CDMA Channel Codec by Configurable Processors," In Intelligent Automation and Soft Computing, volume 12, number 3, pages 317--29, 2006.

[8] Y. Mitsuyama, M. Kimura, T. Onoye, and I. Shirakawa, "Architecture of IEEE802.11i Cipher Algorithms for Embedded Systems," IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, volume E88-A, number 4, pages 899-906, April 2005.

[9] T. Matsumura, N. Iwanaga, W. Kobayashi, T. Onoye, and I. Shirakawa, "Embedded 3D Sound Movement System Based on Feature Extraction of Head-Related Transfer Function," IEEE Transactions on Consumer Electronics, volume 51, number 1, pages 262--267, February 2005.

[10] S. Tani, Y. Uchida, M. Furuie, S. Tsukiyama, B. Lee, S. Nishi, Y. Kubota, I. Shirakawa, and S. Imai, "Parasitic Capacitance Modeling for Non-Planar Interconnects in Liquid Crystal Displays," IEICE Trans. on Fundamentals, volume E86-A, number 12, pages 2923--2932, December 2003.

[11] M. Kimura, M. H. Miki, T. Onoye, and I. Shirakawa, "Implementation of Java Accelerator for High-Performance Embedded Systems," in IEICE Trans. Fundamentals, volume E86-A, number 12, pages 3079--3088, December 2003.

[12] N. Iwanaga, W. Kobayashi, K. Furuya, T. Onoye, and I. Shirakawa, "Embedded Implementation of Acoustic Field Enhancement for Stereo Sound Sources," in IEEE Trans. on Consumer Electronics, volume 49, number 3, pages 737--741, August 2003.

[13] K. Nakagawa, M. Kawakita, K. Sato, M. Minakuchi, T. Onoye, T. Chiba, and I. Shirakawa, "Object Sharing Scheme for Heterogeneous Environment," in IEICE Transaction on Fundamentals of Electronics, Communications and Computer Sciences, volume E86-A, number 4, pages 813--821, April 2003.

[14] N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa, "Single DSP Implementation of Realtime 3D Sound Synthesis Algorithm," Journal of Circuits, Systems and Computers, volume 12, number 1, pages 55-73, February 2003.

[15] H. Mizuno, H. Kobayashi, T. Onoye, and I. Shirakawa, "Performance Estimation at Architecture Level for Embedded Systems," IEEE Transaction on Fundamentals of Electronics, Communications and Computer Sciences, volume E85-A, number 12, pages 2636--2644, December 2002.

[16] Y. Ohtani, N. Kawahara, H. Nakaoka, T. Tomaru K. Maruyama, T. Chiba, T. Onoye, and I. Shirakawa, "Wireless Digital Video Transmission System Using IEEE802.11b PHY with Error Correction Block Based ARQ Protocol," IEICE (Institute of Electronics, Information and Communication Engineers) Transaction on Communications, volume E85-B, number 10, pages 2032--2043, October 2002.

[17] H. Okada, A.-E. Shiitev, H.-S. Song, G. Fujita, T. Onoye, and I. Shirakawa, "Error Detection by Digital Watermarking for MPEG-4 Video Coding," IEICE (Institute of Electronics, Information and Communication Engineers) Transaction on Fundamentals of Electronics, Communications and Computer Sciences, volume E85-A, number 6, pages 1281--1288, June 2002.

[18] M. H. Miki, M. Sakamoto, S. Miyamoto, Y. Takeuchi, T. Yoshida, and I. Shirakawa, "Code Efficiency Evaluation for Embedded Processors," IEICE (Institute of Electronics, Information and Communication Engineers) Transaction on Fundamentals of Electronics, Communications and Computer Sciences, volume E85-A, number 4, pages 811--818, April 2002.

[19] W. Kobayashi, N. Sakamoto, T. Onoye, and I. Shirakawa, "3D Acoustic Image Localization Algorithm by Embedded DSP," IEICE(The Institute of Electronics, Information and Communication Engineers) Trans. Fundamentals of Electronics Communications and Computer Sciences, volume E84-A, number 6, pages 1423--1430, June 2001.

[20] K. Kawamoto, K. Kohno, Y. Higuchi, S. Fujino, and I. Shirakawa, "A 25kV ESD Proof LDMOSFET with a Turn-On Discharge MOSFET," IEICE Trans. Electron, volume E84-C, number 6, pages 823--831, June 2001.

[21] K. Kawamoto, S. Mizuno, H. Abe, Y. Higuchi, H. Ishihara, H. Fukumoto, T. Watanabe, S. Fujino, and I. Shirakawa, "A Single Chip Automotive Control LSI Using SOI Bipolar Complimentary MOS Double-Diffused MOS," The Japan Society of Applied Physics, volume 40, number 4B, pages 2891--2896, April 2001.

[22] Z. Andales, Y. Mitsuyama, T. Onoye, and I. Shirakawa, "A Novel Dynamically Reconfigurable Hardware-Based Cipher," 情報処理学会論文誌, volume 42, number 4, pages 958--966, April 2001.

[23] K. Kawamoto, H. Yamaguchi, H. Himi, S. Fujino, and I. Shirakawa, "A 200 V CMOS SOI IC with Field-Plate Trench Isolation for EL Displays," IEICE Trans. Electron, volume E84-C, number 2, pages 260--266, February 2001.

[24] B.Y. Song, M. Furuie, Y. Yoshida, T. Onoye, and I. Shirakawa, "Low-Power VLSI Implementation by NMOS 4-Phase Dynamic Logic," Trans. of IPSJ, volume 41, number 4, pages 899--907, April 2000.

[25] B.Y. Song, M. Furuie, Y. Yoshida, T. Onoye, and I. Shirakawa, "Low-Power Scheme of NMOS 4-Phase Dynamic Logic," IEICE Trans. Electron., volume E82--C, number 9, pages 1772--1776, September 1999.

[26] H. Fujisima, Y. Takemoto, T. Onoye, and I. Shirakawa, "An Architecture of a Matrix-Vector Multiplier Dedicated to Video Decoding and Three-Dimensional Computer Graphics," IEEE Trans. Circuits and Systems for Video Technology, volume 9, number 2, pages 306--314, March 1999.

[27] A. Nagao, I. Shirakawa, and T. Kambe, "A Layout Approach to Monolithic Microwave IC," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, volume 17, number 12, pages 1262--1272, December 1998.

[28] H. Okuhata, Morgan H. Miki, T. Onoye, and I. Shirakawa, "A Low-Power DSP Core Architecture for Low Bitrate Speech Codec," IEICE Trans. Fundamentals, volume E81-C, number 8, pages 1616--1621, August 1998.

[29] G. Fujita, T. Onoye, and I. Shirakawa, "A VLSI Architecture for Motion Estimation Core Dedicated to H.263 Video Coding," IEICE Trans. Electronics, volume E81-C, number 5, pages 702--707, May 1998.

[30] H. Uno, K. Kumatani, H. Okuhata, I. Shirakawa, and T. Chiba, "ASK Digital Demodulation Scheme for Noise Immune Infrared Data Communication," ACM Wireless Networks, number 3, pages 121-129, 1997.

[31] I. Arungsrisangchai, Y. Shigehiro, I. Shirakawa, and H. Takahashi, "A Fast Minimum Cost Flow Algorithm for Regenerating Optimal Layout of Functional Cells," IEICE Trans. Fundamentals of Electronics,Communications and Computer Sciences, volume E80-A, number 12, pages 2589-2599, December 1997.

[32] K. Miyanohana, G. Fujita, K. Yanagida, T. Onoye, and I. Shirakawa, "Single Chip Implementation of Encoder-Decoder for Low Bit Rate Visural Communication," J. Circuits, Systems, and Computers, volume 7, number 5, pages 441-457, May 1997.

[33] H. Okuhata, H. Uno, K. Kumatani, I. Shirakawa, and T. Chiba, "A Low Power Receiver Architecture for 4 Mbps Infrared Wireless Communication," J. Circuits, Systems, and Computers, volume 7, number 5, pages 483-494, May 1997.

[34] K. Okada, S. Morikawa, S. Takeuchi, and I. Shirakawa, "A High Performance Multiplier and Its Application to an FIR Filter Dedicated to Digital Video Transmission," in Proc. IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, volume E79-A, number 12, pages 2106-2111, December 1996.

[35] Y. Shigehiro, T. Nagata, I. Shirakawa, I. Arungsrisangchai, and H. Takahashi, "Automatic Layout Recycling Based on Layout Description and Linear Programming," in Proc. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, volume 15, number 8, pages 959-967, August 1996.

[36] T. Onoye, G. Fujita, M. Takatsu, I. Shirakawa, and N. Yamai, "Single Chip Implementation of Motion Estimator Dedicated to MPEG2 MP@HL," in Proc. IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences, volume E79-A, number 8, pages 1210-1216, August 1996.

国際会議

[1] S. Takahashi, S. Tsukiyama, M. Hashimoto, and I. Shirakawa, "A Design Method of Finding Optimal Sampling Pulse and Transistor Size in a Sampling Circuit for Liquid Crystal Displays," In In Proceedings of International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), June 2008.

[2] H. Okuhata, K. Takahashi, Y. Nozato, T. Onoye, and I. Shirakawa, "Video Image Enhancement Scheme for High Resolution Consumer Devices," In Proc. of International Symposium on Communications, Control and Signal Processing (ISCCSP2008), pages 639-644, March 2008.

[3] T. Ijichi, M. Hashimoto, S. Takahashi, S. Tsukiyama, and I. Shirakawa, "Transistor Sizing of Lcd Driver Circuit for Technology Migration," In Proceedings of International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), volume 1, I25--I28, July 2006.

[4] Y. Mitsuyama, R. Imai, K. Takahashi, T. Onoye, and I. Shirakawa, "Domain-Specific Reconfigurable Architecture for Media Processing," In Proc. Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI 2006), pages 322--327, April 2006.

[5] Z. Guo, Y. Nishikawa, R. Y. Omaki, T. Onoye, and I. Shirakawa, "A Low-Complexity FEC Assignment Scheme for Motion JPEG2000 Over Wireless Network," In International Conference on Consumer Electronics(ICCE2006), digest of technical papers, Las Vegas, Nevada, USA, pages 391--392, January 2006.

[6] S. Takahashi, A. Taji, S. Tsukiyama, M. Hashimoto, and I. Shirakawa, "A Sampling Switch Design for Liquid Crystal Displays," In Proceedings of IEEE International Region 10 Conference, 1C-03.3, 2005.

[7] S. Takahashi, A. Taji, S. Tsukiyama, M. Hashimoto, and I. Shirakawa, "A Design Scheme for Sampling Switch in Active Matrix LCD," In Proceedings of European Conference on Circuit Theory and Design, 3e-212, 2005.

[8] S. Takahashi, A. Taji, S. Tsukiyama, M. Hashimoto, and I. Shirakawa, "A Sampling Switch Design for Liquid Crystal Displays," In Proceedings of IEEE International Region 10 Conference, November 2005.

[9] S. Takahashi, A. Taji, S. Tsukiyama, M. Hashimoto, and I. Shirakawa, "A Design Scheme for Sampling Switch in Active Matrix Lcd," In A Design Scheme for Sampling Switch in Active Matrix LCD, August 2005.

[10] Huynh Van Nhat, T. Imanaka, G. Fujita, T. Onoye, and I. Shirakawa, "Real-Time Human Object Extraction for Mobile Terminal," In in Proc.The 20th Commemorative International Technical Conference on Circuits/Systems, Computers and Communications(ITC-CSCC2005), Jeju, Korea, volume 3, pages 1015-1016, July 2005.

[11] Y. Mitsuyama, R. Imai, K. Takahashi, T. Onoye, and I. Shirakawa, "An Approach for Area-Efficient Coarse-Grained Reconfigurable Architecture Dedicated to Media Processing," In Proc. International Technical Conference of Circuits/Systems, Computers and Communications (ITC-CSCC2005), pages 131--132, July 2005.

[12] T. Matsumura, N. Iwanaga, T. Onoye, W. Kobayashi, I. Shirakawa, and I. Arungsrisangchai, "3D Sound Movement System for Embedded Applications," In in Proc. IEEE International Symposium on Circuits and Systems (ISCAS2005), Kobe, Japan, pages 5345-5348, May 2005.

[13] Y. Uchida, S. Tani, M. Hashimoto, S. Tsukiyama, and I. Shirakawa, "Interconnect Capacitance Extraction for System LCD Circuits," In in Proc. IEEE/ACM Great Lake Symposium on Very Large Scale Integrated circuits (GLSVLSI 2005), pages 160--163, April 2005.

[14] T. Matsumura, N. Iwanaga, W. Kobayashi, T. Onoye, and I. Shirakawa, "Embedded 3D Sound Movement System Based on Feature Extraction of Head-Related Transfer Function," In in Proc.~International Conference on Consumer Electronics (ICCE2005), digest of technical papers, Las Vegas, Nevada, USA, 7.1-2, January 2005.

[15] N. Iwanaga, W. Kobayashi, K. Furuya, T. Onoye, and I. Shirakawa, "VLSI Implementation of 3D Sound Image Movement for Embedded Systems," In in Proc. IEEE Region 10 Conference (TENCON) 2004, A--021, November 2004.

[16] N. Iwanaga, W. Kobayashi, K. Furuya, T. Onoye, and I. Shirakawa, "VLSI Implementation of a 3D Sound Movement System," In in Proc. The 12th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI) 2004, pages 121-125, October 2004.

[17] Y. Mitsuyama, M. Kimura, T. Onoye, and I. Shirakawa, "Embedded Architecture of IEEE802.11i Cipher Algorithms," In in Proc. 2004 IEEE International Symposium on Consumer Electronics (ISCE2004), pages 241--246, September 2004.

[18] S. Maeta, A. Kosaka, A. Yamada, T. Onoye, T. Chiba, and I. Shirakawa, "C-Based Hardware Design of IMDCT Accelerator for Ogg Vorbis Decoder," In in Proc.12th European Signal Processing Conference (EUSIPCO 2004), pages 1361--1364, September 2004.

[19] Y. Ogasahara, M. Ise, T. Onoye, and I. Shirakawa, "Architecture of Turbo Decoder for W-CDMA by Configurable Processor," In Proc.The 2004 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2004), Sendai, Japan, F2P-27-1--7F2P-27-4, page 7, July 2004.

[20] T. Onoye, H. Tsutsui, G. Fujita, Y. Nakamura, and I. Shirakawa, "Embedded System Implementation of Scalable and Object-Based Video Coding," In in Proc. of World Automation Congress (WAC) , International Forum on Multimedia and Image Processing (IFMIP), IFMIP076, June 2004.

[21] A. Kosaka, S. Yamaguchi, H. Okuhata, T. Onoye, and I. Shirakawa, "SoC Design of Ogg Vorbis Decoder Using Embedded Processor," In in Proc. 2004 Computing Frontier Conference, pages 481--487, April 2004.

[22] K. Hontani, T. Imanaka, G. Fujita, T. Onoye, and I. Shirakawa, "Modified Snake: Real-Time Face Object Extraction for Video Phone," In in Proc. IEEE International Conference on Image Processing(ICIP2003), Barcelona, Spain, volume III, pages 873--876, September 2003.

[23] M. Ise, Y. Ogasahara, T. Onoye, and I. Shirakawa, "Implementation of W-CDMA Channel Codec by Configurable Processors," In Proc. Sixth Baiona Workshop on Signal Processing in Communications, pages 205--210, September 2003.

[24] Y. Uchida, S. Tani, S. Tsukiyama, and I. Shirakawa, "Parasitic Capacitance Modeling for TFT Liquid Crystal Displays," In in Proc. The European Solid-State Device Research Conference (ESSDERC2003) , Estoril, Portugul, pages 453--456, September 2003.

[25] H.-S. Song, H. Okada, G. Fujita, T. Onoye, and I. Shirakawa, "Efficient Error Recovery Scheme for MPEG-4 Video Coding," In in Proc. The 2003 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2003), Kang-Woo Do, Korea, volume 2, pages 1328--1331, July 2003.

[26] Y. Uchida, S. Tani, S. Tsukiyama, and I. Shirakawa, "Parasitic Capacitance Modeling for On-Chip Interconnects," In in Proc. The 2003 International Technical Conference on Circuits/Systems, Computers and ommunications (ITC-CSCC2003) , Kang-Woo Do, Korea, volume 3, pages 1638--1641, July 2003.

[27] S. Yamaguchi, A. Kosaka, H. Okuhata, T. Onoye, and I. Shirakawa, "Low Power Ogg Vorbis Decoder by Embedded Processor," In in Proc. The 2003 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2003), Kang-Woo Do, Korea, volume 1, pages 565--568, July 2003.

[28] T. Matsumura, N. Iwanaga, W. Kobayashi, T. Onoye, and I. Shirakawa, "Feature Extraction of Head-Related Transfer Function for 3D Sound Movement," In in Proc. The 2003 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2003), Kang-Woo Do, Korea, volume 1, pages 685--688, July 2003.

[29] N. Iwanaga, W. Kobayashi, K. Furuya, T. Onoye, and I. Shirakawa, "Embedded Implementation of Acoustic Field Enhancement for Stereo Sound Sources," In in IEEE 29th International Conference on Consumer Electronics (ICCE2003), digest of technical papers, Los Angeles, Carifornia, USA, pages 256--257, June 2003.

[30] T. Okada, T. Uchida, T. Onoye, and I. Shirakawa, "A Novel Signal Processing Scheme for Next Generation GNSS Receiver," In in Proc. the 8th ISU International Symposium, Strasbourg, France, May 2003.

[31] S. Komata, A. Pal, N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa, "Interactive Interface of Realtime 3D Sound Movement for Embedded Applications," In in Proc. IEEE International Symposium on Circuits and Systems (ISCAS2003) , Bankok, Thailand, volume II, pages 520--523, May 2003.

[32] T. Okada, T. Uchida, T. Onoye, and I. Shirakawa, "A Novel Signal Processing Scheme for Next Generation GNSS Receiver and Its VLSI Implementation," In in Proc. International Signal Processing Conference , Dallas, number 357, April 2003.

[33] N. Iwanaga, W. Kobayashi, K. Furuya, N. Sakamoto, T. Onoye, and I.Shirakawa, "Low Cost Approach to Acoustic Field Enhancement for Stereo Headphones," In in Proc. Euromedia 2003, Plymouth, United Kingdom, pages 32--36, April 2003.

[34] S. Tani, Y. Uchida, M. Furuie, S. Tsukiyama, B. Lee, S. Nishi, Y. Kubota, I. Shirakawa, and S. Imai, "A Parasitic Capacitance Modeling Method for Non-Planar Interconnects," In in Proc. the Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI 2003), pages 294--299, April 2003.

[35] T. Nakagawa, G. Fujita, T. Onoye, and I. Shirakawa, "Vlsi Architecture for Mpeg-4 Core Profile Codec Core," In Proc. Workshop on Synthesis and System Integration of Mixed Information Technologies, pages 365--371, April 2003.

[36] K. Hontani, T. Imanaka, G. Fujita, T. Onoye, and I. Shirakawa, "Realtime Face Object Extraction Algorithm for Video Phone," In in Proc. IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2002), Orchard Road, Singapore, volume 1, pages 35--38, December 2002.

[37] Y. Ohtani, H. Nakaoka, T. Tomaru, K. Maruyama, T. Chiba, T. Onoye, and I. Shirakawa, "Implementation of Wireless MPEG2 Transmission System Using IEEE 802.11b PHY," In ibid, volume 1, pages 39--44, December 2002.

[38] N. Iwanaga, W. Kobayashi, K. Furuya, N. Sakamoto, T. Onoye, and I. Shirakawa, "Embedded Implementation of Acousitic Field Enhancement for Stereo Headphones," In ibid, volume 1, pages 51--54, December 2002.

[39] S. Tani, Y. Uchida, M. Furuie, S. Tsukiyama, B. Lee, S. Nishi, Y. Kubota, I. Shirakawa, and S. Imai, "Parasitic Capacitance Modeling for Multilevel Interconnects," In in Proc. IEEE Proceedings of Asia-Pacific Conference on Circuits and Systems 2002, volume 1, pages 59--64, December 2002.

[40] A. Kosaka, S. Yamaguchi, H. Okuhata, T. Onoye, and I. Shirakawa, "VLSI Implementation of Ogg Vorbis Decoder for Embedded Applications," In in Proc. 15th Annual IEEE International ASIC/SoC Conference(ASIC/SoC2002), Rochester, N.Y., pages 20--24, September 2002.

[41] A. Kosaka, S. Yamaguchi, H. Okuhata, T. Onoye, and I. Shirakawa, "A Hardware Implementation of Ogg Vorbis Audio Decoder with Embedded Processor," In in Proc. 17th Annual International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2002), Phuket, Thailand, pages 94--97, July 2002.

[42] S. Komata, N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa, "Synthesis of 3D Sound Movement by Embedded DSP," In ibid, pages 117--120, July 2002.

[43] H. Okada, A.-E. Shiitev, H.-S. Song, G. Fujita, T. Onoye, and I. Shirakawa, "Digital Watermark Based Error Detection for MPEG-4 Bitstream Error," In ibid, pages 152--155, July 2002.

[44] T. Kaya, R. Miyamoto, T. Onoye, and I. Shirakawa, "Embedded System for Video Coding with Logic-Enhanced DRAM and Configurable Processor," In ibid, pages 216--219, July 2002.

[45] H.-S. Song, H. Okada, G. Fujita, T. Onoye, and I. Shirakawa, "Hybrid Error Concealment Algorithm for MPEG-4 Videodecoders," In ibid, pages 611--614, July 2002.

[46] K. Nakagawa, M. Kawakita, K. Sato, M. Minakuchi, O. Tsumori, K. Hanada, T. Chiba, and I. Shirakawa, "OCEAN: Object Communication Environment for Arbitrary Network," In in Proc. IEEE International Conference on Distributed Computing Systems Workshops, pages 162--166, July 2002.

[47] W. Kobayashi, K. Furuya, N. Sakamoto, T. Onoye, and I. Shirakawa, "`Out-Of-Head' Acoustic Field Enhancement for Stereo Headphones by Embedded DSP," In in IEEE 28th International Conference on Consumer Electronics (ICCE2002), digest of technical papers, Cardiff, Wales, pages 222--223, June 2002.

[48] Y. Ohtani, N. Kawahara, T. Onoye, I. Shirakawa, and T. Chiba, "MAC LSI Design for Wireless MPEG2 Transmission Over IEEE802.11b PHY," In ibid, pages 242--243, June 2002.

[49] Y. Mitsuyama, Z. Andales, T. Onoye, and I. Shirakawa, "Burst Mode: a New Acceleration Mode for 128-Bit Block Ciphers," In in Proc. IEEE 24th Custom Integrated Circuits Conference (CICC2002), Orland, Florida, pages 151--154, May 2002.

[50] Y. Uchida, M. Ise, T. Onoye, I. Shirakawa, and I. Arungsrisangchai, "VLSI Architecture of Digital Matched Filter and Prime Interleaver for W-CDMA," In Proc. IEEE International Symposium on Circuits and Systems (ISCAS2002), Phoenix, Arizona, volume III, pages 269--272, May 2002.

[51] Y. Mitsuyama, Z. Andales, T. Onoye, I. Shirakawa, and I. Arungsrisangchai, "VLSI Architecture of Burst Mode Acceleration for 128-Bit Block Ciphers," In ibid, volume II, pages 344--347, May 2002.

[52] H. Mizuno, H. Kobayashi, T. Onoye, and I. Shirakawa, "Power Estimation at Architecture Level for Embedded Systems," In ibid, volume II, pages 476--479, May 2002.

[53] Y. Ohtani, N. Kawahara, T. Tomaru, K. Maruyama, T. Onoye, I. Shirakawa, and T. Chiba, "Error Correction Block Based ARQ Protocol for Wireless Digital Video Transmission," In ibid, volume I, pages 605--608, May 2002.

[54] M. Kimura, M. H. Miki, T. Onoye, and I. Shirakawa, "A Java Accelerator for High Performance Embedded Systems," In in Proc. 4th International Conference of Massively Parallel Computing Systems (MPCS 2002), Ischia, Italy, 2, April 2002.

[55] N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa, "DSP Implementation of Realtime 3D Sound Synthesis Algorithm for Monaural Sound Source," In in Proc. EUROMEDIA 2002, Modena, Italy, pages 123--127, April 2002.

[56] M. H. Miki, M. Kimura, T. Onoye, and I. Shirakawa, "High Performance Java Hardware Engine and Software Kernel for Embedded Systems," In in Proc. 11th IFIP International Conference on Very Large Scale Integration (VLSI-SOC 2001), Montpellier-Le Corum, France, pages 365--369, December 2001.

[57] H. Mizuno, H. Kobayashi, T. Onoye, and I. Shirakawa, "An Architecture Level Power Estimation Method for Embedded Systems," In in Proc. Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI 2001), Nara, Japan, pages 78--85, October 2001.

[58] Z. Andales, Y. Mitsuyama, T. Onoye, and I. Shirakawa, "System Performance Evaluation of High-Speed Burst Mode for 128-Bit Block Ciphers," In in Proc. Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI 2001), Nara, Japan, pages 332--339, October 2001.

[59] M. Kimura, M. H. Miki, T. Onoye, and I. Shirakawa, "High Performance Java Execution for Embedded Systems," In in Proc. Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI 2001), Nara, Japan, pages 346--350, October 2001.

[60] M. Ise, Y. Uchida, T. Onoye, and I. Shirakawa, "System-On-A-Chip Architecture for W-CDMA Baseband Modem LSI," In in Proc. The 4th International Conference on ASIC (ASICON 2001), Shanghai, pages 364--369, October 2001.

[61] M. Furuie, T. Onoye, S. Tsukiyama, and I. Shirakawa, "Two-Dimensional Array Layout for NMOS 4-Phase Dynamic Logic," In in Proc. The 8th IEEE International Conference on Electronics, Circuits and Systems(ICECS 2001), Malta, pages 589--592, September 2001.

[62] N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa, "DSP Implementaion of 3D Sound Localization Algorithm for Monaural Sound Source," In in Proc. The 8th IEEE International Conference on Electronics, Circuits and Systems(ICECS 2001), Malta, pages 1061--1064, September 2001.

[63] N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa, "DSP Implementation of Low Computational 3D Sound Localization Algorithm," In in Proc. 200l IEEE Workshop on Signal Processing Systems, Design and Implementation(SIPS 2001), Antwerp, Belgium, pages 109--116, September 2001.

[64] Y. Mitsuyama, Z. Andales, T. Onoye, and I. Shirakawa, "VLSI Implementation of High Performance Burst Mode for 128-Bit Block Ciphers," In in Proc. 14th Annual IEEE International ASIC/SoC Conference (ASIC/SoC2001), Washington, D.C., pp. W.1.1.1--W.1.1.5, September 2001.

[65] H. Okada, H. S. Song, G. Fujita, T. Onoye, and I. Shirakawa, "Error Detection Based on Check Marker Embedding for MPEG-4 Video Coding," In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC '01), Tokushima, Japan, pages 96--99, July 2001.

[66] H. S. Song, H. Okada, G. Fujita, T. Onoye, and I. Shirakawa, "Error Concealment Algorithm by Motion Estimation Method for MPEG-4 Video Decoder," In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC '01), Tokushima, Japan, pages 104--107, July 2001.

[67] T. Song, G. Fujita, T. Onoye, and I. Shirakawa, "Low Power Architecture for H.263 Version2 Codec," In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC '01), Tokushima, Japan, pages 620--623, July 2001.

[68] N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa, "DSP Implementation of Realtime 3D Sound Localization Algorithm," In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC '01), Tokushima, Japan, pages 1140--1143, July 2001.

[69] N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa, "Low Power DSP Implementation of 3D Sound Localization for Monaural Sound Source," In in Proc. World Multiconference on Systemics, Cybernetics and Informatics (SCI 2001), Orlando, Florida, USA, pages 173--177, July 2001.

[70] M. H. Miki, M. Sakamoto, S. Miyamoto, Y. Takeuchi, T. Yoshida, and I. Shirakawa, "Evaluation of Processor Code Efficiency for Embedded Systems," In in Proc. ACM 15th International Conference on Supercomputing, Sorrento, Italy, pages 229--235, June 2001.

[71] Y. Mitsuyama, Z. Andales, T. Onoye, and I. Shirakawa, "VLSI Architecture of Dynamically Reconfigurable Hardware-Based Cipher," In in Proc. IEEE International Symposium on Circuits and Systems (ISCAS2001) , Sydney, Australia, volume IV, pages 734--737, May 2001.

[72] Z. Andales, Y. Mitsuyama, T. Onoye, and I. Shirakawa, "A High Performance Burst Mode Approach for 128-Bit Block Ciphers," In in Proc. EUROMEDIA2001, Valencia, Spain, pages 146--150, April 2001.

[73] Y. Mitsuyama, Z. Andales, T. Onoye, and I. Shirakawa, "A Dynamically Reconfigurable Hardware-Based Cipher Chip," In in Proc. Asia and South Pacific Design Automation Conference (ASP-DAC 2001), Yokohama, Japan, pages 11--12, January 2001.

[74] R. Y. Omaki, Y. Dong, M. H. Miki, M. Furuie, D. Taki, M. Tarui, G. Fujita, T. Onoye, and I. Shirakawa, "Realtime Wavelet Video Coder Based on Reduced Memory Accessing," In in Proc.~Asia and South Pacific Design Automation Conference (ASP-DAC 2001), Yokohama, Japan, pages 15--16, January 2001.

[75] S. Hashimoto, A. Niwa, H. Okuhata, T. Onoye, and I. Shirakawa, "VLSI Implementation of Portable MPEG-4 Audio Decoder," In in Proc. International ASIC/SOC Conference (ASIC/SOC 2000), Arington, VA, USA, pages 80--84, September 2000.

[76] Y. Dong, R. Y. Omaki, T. Onoye, and I. Shirakawa, "VLSI Implementation of a Reduced Memory Bandwidth Realtime EZW Video Coder," In in Proc. International Conference on Image Processing (ICIP 2000), volume III, pages 126--129, September 2000.

[77] K. Kawamoto, S. Mizuno, H. Abe, Y. Higuchi, S. Fujino, and I. Shirakawa, "A Shingle Chip Automotive Control LSI Using SOI BiCDMOS," In in Proc. of 2000 International Conference on Solid State Device and Materials, pages 486-487, August 2000.

[78] N. Sakamoto, W. Kobayashi, T. Onoye, and I. Shirakawa, "Low Power DSP Implementation of 3D Sound Localization," In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2000), Pusan, Korea, pages 253--256, July 2000.

[79] W. Kobayashi, N. Sakamoto, T. Onoye, and I. Shirakawa, "3D Acoustic Image Localization Algorithm by Embedded DSP," In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2000), Pusan, Korea, pages 264--267, July 2000.

[80] R. Kuroda, G. Fujita, T. Onoye, and I. Shirakawa, "Discrete Cosine Transformer with Variable-Length Basis Vector for MPEG-4 Video Codec," In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2000), Pusan, Korea, pages 811--814, July 2000.

[81] Y. Mitsuyama, Z. Andales, T. Onoye, and I. Shirakawa, "VLSI Implementation of Dynamically Reconfigurable Hardware-Based Cryptosystem," In in Symposium on VLSI Circuits Digest of Technical Papers, Hawaii, USA, pages 204--205, June 2000.

[82] Z. Andales, Y. Mitsuyama, T. Onoye, and I. Shirakawa, "Chameleon: a Dynamically Reconfigurable Hardware-Based Cryptosystem," In in Proc. EUROMEDIA2000 , Antwerp, Belgium, pages 90--94, May 2000.

[83] R. Y. Omaki, Y. Dong, M. H. Miki, M. Furuie, S. Yamada, D. Taki, M. Tarui, G. Fujita, T. Onoye, and I. Shirakawa, "VLSI Implementation of a Realtime Wavelet Video Coder," In in Proc. Custom Integrated Circuits Conference (CICC 2000), Florida, USA, pages 543--546, May 2000.

[84] M. Furuie, B. Y. Song, Y. Yoshida, T. Onoye, and I. Shirakawa, "Layout Generation of Array Cell for NMOS 4-Phase Dynamil Logic," In in Proc. ASP-DAC2000, pages 529--532, January 2000.

[85] R. Y. Omaki, G. Fujita, T. Onoye, and I. Shirakawa, "Video Coding Algorithm Based on Modified Discrete Wavelet Transform," In in Proc. NOLTA'99, volume I, pages 251--254, November 1999.

[86] R. Y. Omaki, G. Fujita, T. Onoye, and I. Shirakawa, "Architecture of Embedded Zerotree Wavelet Based Real-Time Video Coder," In in Proc. 12th IEEE ASIC/SOC Conference, pages 137-141, October 1999.

[87] R. Y. Omaki, G. Fujita, T. Onoye, and I. Shirakawa, "Embedded Zerotree Wavelet Based Algorithm for Video Compression," In in Proc. IEEE Region 10 Conference (TENCON '99), pp.II-1343--1346, September 1999.

[88] M. Furuie, B. Y. Song, Y. Yoshida, T. Onoye, and I. Shirakawa, "Layout Generation for Low-Power NMOS 4-Phase Dynamic Logic Array," In in Proc. IEEE Region 10 Conference (TENCON '99), pages 872--875, September 1999.

[89] M. Tarui, M. Oshita, T. Onoye, and I. Shirakawa, "High-Speed Implementation of JBIG Arithmetic Coder," In in Proc. IEEE Region 10 Conference (TENCON '99), pages 1291--1294, September 1999.

[90] B. Y. Song, M. Furuie, Y. Yoshida, T. Onoye, and I. Shirakawa, "Array Macro Cell Architecture for Low-Power NMOS 4-Phase Dynamic Logic," In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC '99), Sado, Japan, pages 561--564, July 1999.

[91] M. Oshita, M. Tarui, T. Onoye, and I. Shirakawa, "Pipelined Implementation of JBIG Arithmetic Coder," In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC '99), Sado, Japan, pages 470--473, July 1999.

[92] M. H. Miki, D. Taki, G. Fujita, T. Onoye, I. Shirakawa, T. Fujiwara, and T. Kasami, "Recursive Maximum Likelihood Decoder for High-Speed Satellite Communication," In in Proc. IEEE International Symposium on Circuits and Systems (ISCAS '99) , Orland, USA, volume IV, pages 572--575, June 1999.

[93] H. Fujishima, Y. Takemoto, T. Yoneda, T. Onoye, and I. Shirakawa, "Hybrid Media-Processor Core for Natural and Synthetic Video Decoding," In in Proc. IEEE International Symposium on Circuits and Systems (ISCAS '99) , Orland, USA, volume IV, pages 275--278, June 1999.

[94] G. Fujita, H. Okuhata, M. H. Miki, T. Onoye, and I. Shirakawa, "Low-Power Architecture of H.324 Codec Dedicated to Mobile Computing," In in Proc. EUROMEDIA'99 , Munich, Germany, pages 145--149, April 1999.

[95] K. Asari, Y. Mitsuyama, T. Onoye, I. Shirakawa, H. Hirano, T. Honda, T. Otsuki, T. Baba, and T. Meng, "Multi-Mode and Multi-Level Technologies for FeRAM Embedded Reconfigurable Hardware," In in Proc. IEEE Internatinal Solid-State Circuits Conference, pages 106--107, February 1999.

[96] H. Fujisima, Y. Takemoto, T. Yoneda, T. Onoye, and I. Shirakawa, "Hybrid VLSI Architecture for Motion Compensation and Texture Mapping," In in Proc. IEEE International Workshop on Intelligent Signal Processing and Communication Systems, pages 383--386, November 1998.

[97] J. Fan, G. Fujita, M. Furuie, T. Onoye, and I. Shirakawa, "Structual Objeco-Oriented Video Segmentation and Representation Algorithm," In in Proc. IEEE International Workshop on Intelligent Signal Processing and Communication Systems, pages 78--82, November 1998.

[98] H. Fujisima, Y. Takemoto, T. Onoye, I. Shirakawa, and K. Matsumura, "Matrix-Vector Multiplier Module for Natural/Synthetic Hybrid Video Coding," In in Proc. IEEE Asia Pacific Conference on Circuits and Systems, pages 631--634, November 1998.

[99] B.Y. Song, Y. Yoshida, T. Onoye, and I. Shirakawa, "Low-Power Implementation by a New Logic Scheme of NMOS 4-Phase Dynamic Logic," In in Proc. Workshop on Synthesis and System Integration of Mixed Technologies, pages 235--240, October 1998.

[100] B.Y. Song, Y. Yoshida, T. Onoye, and I. Shirakawa, "Delay and Power Simulation for a New Logic Scheme of NMOS 4-Phase Dynamic Logic," In in Proc. European Simulation Symposium, pages 339--343, October 1998.

[101] J. Fan, G. Fujita, J. Yu, K. Miyanohana, T. Onoye, N. Ishiura, L. Wu, and I. Shirakawa, "Hierarchical Object-Oriented Image and Video Segmentation Algorithm Based on 2D Entropic Thresholding," In in Proc. Electronic Imaging and Multimedia Systems II, SPIE, pages 141--151, September 1998.

[102] K. Matsumura, G. Fujita, I. Shirakawa, and H. Inada, "A Wireless Data System Constructed of SAW-Based Receiver/Transmitter and Its Applications to Medical Cares," In in Proc. IEEE Radio & Wireless Conf., pages 47--50, August 1998.

[103] Y. Takemoto, T. Yoneda, H. Fujishima, T. Onoye, and I. Shirakawa, "VLSI Implementation of Function Module for Texture Mapping and Motion Compensation," In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications, pages 179--182, July 1998.

[104] R. Y. Omaki, G. Fujita, T. Onoye, and I. Shirakawa, "Implementation of DWT and EZW Cores for a Bitrate Scalable Video Coder," In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications, pages 221--224, July 1998.

[105] K. Matsumura, G. Fujita, I. Shirakawa, and H. Inada, "A Wireless Data System by Means of SAW-Based Transmitter/Receiver and Its Applications to Medical Cares," In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications, pages 299--302, July 1998.

[106] H. Fujisima, Y. Takemoto, T. Onoye, and I. Shirakawa, "Matrix-Vector Multiplier for Natural/Synthetic Hybrid Video Coding," In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications, pages 1269--1272, July 1998.

[107] D. Taki, G. Fujita, T. Onoye, I. Shirakawa, T. Fujiwara, and T. Kasami, "VLSI Implementation of a Recursive Maximum Likelihood Decoder for High-Speed Satellite Communication," In in Proc. International Technical Conference on Circuits/Systems, Computers and Communications, pages 1383--1386, July 1998.

[108] K. Matsumura, G. Fujita, I. Shirakawa, and H. Inada, "A Wireless Data Systems Constructed of SAW-Divices and Its Applications to Medical Cares," In in Proc. Analog VLSI WS, pages 39--44, June 1998.

[109] G. Fujita, H. Okuhata, M. H. Miki, T. Onoye, and I. Shirakawa, "Implementation of H.324 Audiovisual Codec for Mobile Computing," In in Proc. IEEE Custom Integrated Circuits Conference, pages 193--196, May 1998.

[110] H. Okuhata, M. H. Miki, T. Onoye, and I. Shirakawa, "A Low Power DSP Core Architecture for Low Bitrate Speech Codec," In in Proc. IEEE Int'l Conf. Acoustics, Sounds, and Signal Processing, pages 3121--3124, May 1998.

[111] T. Onoye, G. Fujita, H. Okuhata, M. H. Miki, and I. Shirakawa, "Low-Power Implementation of H.324 Audiovisual Codec Dedicated to Mobile Computing," In in Proc. Aia and South Pacific Design Automation Conference (ASP-DAC '98), pages 589-594, February 1998.

[112] H. Fujishima, Y. Takemoto, T. Onoye, I. Shirakawa, and S. Sakaguchi, "A Unified Media-Processor Architecure for Video Coding and Computer Graphics," In in Proc. International Workshop on Synthetic-Natural Hybrid Coding and Three Dimensional Imaging, pages 253-256, September 1997.

[113] H. Uno, K. Kumatani, H. Okuhata, T. Chiba, and I. Shirakawa, "Low Power Architecture for High Speed Infrared Wireless Communication System," In in Proc.International Symposium on Low Power Electronics and Design, pages 255-258, August 1997.

[114] Y. Yoshida, B. Y. Song, H. Okuhata, T. Onoye, and I. Shirakawa, "An Object Code Compression Approach to Embedded Processors," In in Proc. International Symposium on Low Power Electronics and Design, pages 265-268, August 1997.

[115] H. Fujisima, Y. Takemoto, T. Onoye, and I. Shirakawa, "Media-Processor Architecture Unified for Video Coding and 3D Graphics," In in Proc. Int'l Technical Conference on Circuit/Systems, Computers and Communications, pages 1223-1226, July 1997.

[116] I. Arungsrisangchai, Y. Shigehiro, I. Shirakawa, and H. Takahashi, "A Fast Minimun Cost Flow Algofithm for VLSI Layout Compaction," In in Proc. IEEE International Symposium on Circuits and Systems, pages 1672-1675, June 1997.

[117] K. Miyanohana, G. Fujita, K. Yanagida, T. Onoye, and I. Shirakawa, "VLSI Implementation of Single Chip Encoder/Decoder for Low Bitrate Visual Communication," In in Proc. IEEE Custom Integrated Circuits Conference, pages 229-232, May 1997.

[118] H. Okuhata, H. Uno, K. Kumatani, I. Shirakawa, and T. Chiba, "A 4Mbps Infrared Wireless Link Dedicated to Mobile Computing," In in Proc. IEEE International Performance, Computing, and Communications Conference, pages 463-467, February 1997.

[119] S. Morikawa, K. Okada, S. Takeuchi, and I. Shirakawa, "A High Performance FIR Filter Dedicated to Digital Video Transmission," In in Proc. IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC '97), pages 77-82, January 1997.

[120] G. Fujita, T. Onoye, I. Shirakawa, S. Tsukiyama, and K. Matsumura, "Implementation of Half-Pel Precision Motion Estimator for MPEG2 MP@HL," In in Proc. IEEE Region 10 International Conference on Digital Signal Processing Applications (TENCON '96), pages 949-954, November 1996.

[121] H. Uno, K. Kumatani, H. Okuhata, I. Shirakawa, and T. Chiba, "A 4Mbps Infrared Wireless Communication System Dedicated to Mobile Computing," In in Proc. IEEE Asia Pacific Conference on Circuits and Systems (APCCAS '96), pages 334-337, November 1996.

[122] K. Miyanohana, G. Fujita, T. Onoye, and I. Shirakawa, "VLSI Implementation of Edge Detector and Vector Quantizer for Very Low Bitrate Video Encoding," In in Proc. IEEE Asia Pacific Conference on Circuits and Systems (APCCAS '96), pages 480-483, November 1996.

[123] Y. Yoshida, B. Y. Song, H. Okuhata, T. Onoye, and I. Shirakawa, "Low-Power Consumption Architecture for Embedded Processor," In in Proc. 2nd International Conference on ASIC, pages 77-80, October 1996.

[124] K. Miyanohana, G. Fujita, T. Onoye, and I. Shirakawa, "Implementation of Very Low Bitrate Video Encoder Core," In in Proc. 2nd International Conference on ASIC, pages 131-134, October 1996.

[125] T. Onoye, G. Fujita, M. Takatsu, I. Shirakawa, and K. Matsumura, "A Single Chip Motion Estimator Dedicated to MPEG2 MP@HL," In in Proc. European Signal Processing Conference, pages 1479-1482, September 1996.

[126] G. Fujita, H. Okuhata, Y. Nakatani, T. Onoye, and I. Shirakawa, "Single Chip MPEG2 MP@ML Motion Estimator," In in Proc. Int'l Technical Conference on Circuits/Systems, Computers and Communications, pages 286-289, July 1996.

[127] K. Miyanohana, G. Fujita, T. Onoye, and I. Shirakawa, "VLSI Architecture for Very Low Bitrate Video Encoder Core," In in Proc. Int'l Technical Conference on Circuits/Systems, Computers and Communications, pages 294-297, July 1996.

[128] S. Nakamura, N. Ishiura, T. Yamamoto, and I. Shirakawa, "High-Level Synthesis System for Behavioral Descriptions with Conditional Branches," In in Proc. Int'l Technical Conference on Circuits/Systems, Computers and Communications, pages 935-938, July 1996.

[129] Y. Shigehiro, I. Shirakawa, I. Arungsrisangchai, and H. Takahashi, "A Fast Minimum Cost Flow Algorithm and Its Application to VLSI Layout Compaction," In in Proc. Int'l Technical Conference on Circuits/Systems, Computers and Communications, pages 951-954, July 1996.

[130] H. Uno, K. Kumatani, H. Okuhata, T. Masaki, I. Shirakawa, and T. Chiba, "A 4Mbps Infrared Wireless Communication Link for Mobile Computing," In in Proc. Workshop on Multi-Dimensional Mobile Communications (MDMC '96), pages 267-271, July 1996.

[131] T. Onoye, G. Fujita, M. Takatsu, I. Shirakawa, K. Matsumura, H. Ariyoshi, and S. Tsukiyama, "VLSI Implementation of Hierarchical Motion Estimator for MPEG2 MP@HL," In in Proc. IEEE Custom Integrated Circuits Conference, pages 351-354, May 1996.

[132] T. Onoye, G. Fujita, M. Takatsu, I. Shirakawa, K. Matsumura, H. Ariyoshi, and S. Tsukiyama, "A VLSI Architecture of MPEG2 MP@HL Motion Estimator," In in Proc. IEEE Int'l Symposium on Circuits and Systems, pages 664-667, May 1996.

[133] K. Itoh, Y. Shigehiro, I. Shirakawa, and K. Matsumura, "An Approach for Multi-Layer Gridless Routing," In in Proc. Printed Circuit World Convention VII, pp.P2-1-P2-7, May 1996.

研究会等発表論文

[1] 伊勢正尚, 小笠原泰弘, 渡邊賢治, 畠中理英, 尾上孝雄, 庭本浩明, 芥子育雄, 白川功, "IEEE 802.15.4を用いたホームネットワーク向け無線ネットワークプロトコル," 信学技報, CAS2005-99, pages 19--24, 2006年3月.

[2] 渡邊賢治, 伊勢正尚, 藤田玄, 畠中理英, 尾上孝雄, 庭本浩明, 芥子育雄, 白川功, "無線ホームネットワークにおける消費電力および即時性の改善手法," 信学技報, CAS2005-100, pages 25--30, 2006年3月.